XML2VHDL Logo

Basics

  • Nomenclature
    • Active-low signals
      • Concepts
    • Node types
    • Sides
    • Host design
      • VHDL libraries
    • Bus Library
    • XML Linked Library
    • Linking
  • Development Flow
    • Generation Methods
    • Software Support
  • File Descriptions
    • Relationships
    • Input
    • Output
  • XML Descriptions
    • Register Maps
      • Node Attributes
        • Top-Level
        • Entries
      • Considerations
    • Interconnects
      • Node Attributes
        • Top-Level
        • Entries
      • Considerations
    • Internal Memory
      • Node Attributes
      • Considerations
    • External Memory
      • Node Attributes
      • Considerations
    • Generated Output
      • Considerations
  • Implementation
    • Register Maps
      • VHDL Output
        • Package File Entries
        • Top-level Component
        • Example Instantiation
    • Interconnects
      • VHDL Output
        • Package File Entries
        • Top-level Component
        • Example Instantiation

Usage

  • Installation
  • Running
    • Help Message
  • Python Modules
    • Classes
      • Xml2VhdlGenerate
      • Xml2Vhdl

Advanced Usage

  • Memories and Arrays
    • External Memory
      • External Memory Wrapper
    • Arrays
    • Internal & External Memory
  • External Memory-Mapped Components
    • Linking to an Interconnect
    • Connecting to Logic-side

Documentation Tools

  • XML 2 Docs
    • Setup
      • Sphinx Extension
      • CLI Interface
        • Named Arguments
    • Using Built Restructured Text Documentation
  • XML 2 Dict
    • Usage
    • Dictionary Keys
      • Nodes
      • Registers
        • field_list dict
      • Bitfields
    • Formats
      • Human Readable Format
      • Upper Format
      • Lower Format
    • Merging Registers
    • Collapsing Nodes

References

  • Example Generated Components
    • Required Libraries
    • axi4lite_REGISTERMAP_XML_NODENAME
      • Block Diagram
      • Port Descriptions
        • AXI4-Lite interface
        • Records to connect to/from user logic
      • Usage
        • Library Declarations
        • Signal Declarations
        • Component Instantiation
    • axi4lite_REGISTERMAP_XML_NODENAME_muxdemux
      • Block Diagram
      • Port Descriptions
        • Clocks and Resets
        • IPbus - Secondary-Side
        • IPbus Array - Primary-Side
    • axi4lite_IC_XML_NODENAME_ic
      • Block Diagram
      • Port Descriptions
        • AXI4-Lite interface
        • AXI4-Lite interface array
      • Usage
        • Library declarations
        • Signal declarations
        • Component instantiation
        • Referencing array IDs
  • Reserved VHDL Keywords
  • Support Files
  • Links
    • SKAO Specific
  • Glossary
    • Abbreviations
    • Terms
  • Version History
    • Unreleased
    • 0.8.1
    • 0.8.0
    • 0.7.0
    • 0.6.5
    • 0.6.4
    • 0.6.3
    • 0.6.2
    • 0.6.1
    • 0.6.0
    • 0.5.0
    • 0.4.1
    • 0.4.0
    • 0.3.0
    • 0.2.6
    • 0.2.0
    • 0.1.16
    • 0.1.15
    • 0.1.14
    • 0.1.13
    • 0.1.12
    • 0.1.11
    • 0.1.10
    • 0.1.9
    • 0.1.8
    • 0.1.7
    • 0.1.6
    • 0.1.5
    • 0.1.4
    • 0.1.3
    • 0.1.2
    • 0.1.1
    • 0.1.0
XML2VHDL
  • Search

© Copyright 2025 UNITED KINGDOM RESEARCH AND INNOVATION Electronic System Design Group, Technology Department, Science and Technology Facilities Council.

Built with Sphinx using a theme provided by Read the Docs.