Development Flow

Generally, the end-user will develop and define the host design memory-map using a bottom-to-top approach. It is expected that larger designs will leverage pre-defined XML2VHDL descriptions for reusable components with the potential to integrate memory-mapped FPGA vendor IP into the final design.

  1. The end-user defines XML Register Maps for each element [module] in the host design. If required, these design elements may require the definition of Interconnects to logically group Register Maps by function (i.e. separating status and control registers).

    Tip

    The calculated total address-space can be checked using the byte_size= node attribute in the generated XML output file for each Register Map description. This can be used to determine address-offset values in Interconnect descriptions.

  2. Process the XML input files using XML2VHDL, ensuring the output VHDL is associated with the correct VHDL libraries (via the --bus_library|--slave_library arguments).

  3. The end-user is required to manually integrate the resulting VHDL into the host design, by making Bus-side connections between Interconnects and other Interconnects and/or Register Maps. The end-user also needs to expand and connect to/from Register Maps on the Logic-side as required.

  4. Repeat steps 1-3 as necessary.

  5. Add the selected BUS_LINKED_LIB VHDL support package(s) and components to the FPGAFirmware project.

    For AXI4-Lite these will be the equivalent of [axi4_lib] ../support_files/axi4lite_pkg.vhd and ../support_files/axi4lite_slave_logic.vhd

  6. Add the generated VHDL components and package files to the FPGA Firmware project.

    Attention

    Ensure these files are assigned to the correct VHDL libraries.

  7. Once all of the generated VHDL components and support packages have been added to the FPGA Firmware project, it can be compiled to generate the Bitstream file.

  8. Optional. Assuming the target FPGA Hardware and associated control-plane Software has a mechanism to retrieve and extract the contents. It is possible to embed XML2VHDLHEX file of the top-level description into a FPGA BRAM (or equivalent). This allows the FPGA to self-describe its own address-space.

    In this case, it is the responsibility of the software to retrieve, and extract, this address-space description. The software can then determine what features to support on the target Hardware. The physical addresses remain transparent to the software, with registers/register child bit-fields being referenced by name instead.

    Note

    The advantage of having a transparent physical address is that it improves development, making it more flexible and less error prone.

Generation Methods

Various methods for managing the generation of XML2VHDL memory-maps are possible.

  • Directly, via the Command Line Interface.

  • Linux BASH scripts.

  • Scripted FPGA build - including using pre-synthesis hooks.

  • Scripted, called during Continuous Integration work-flows.

  • Using project specific GUI tools.

Attention

To ensure the most recent versions of address-spaces are generated, it is recommended to automate the generation of XML2VHDL output prior to compiling the FPGA Firmware project.

Software Support

Tip

In parallel to the FPGA Firmware development, it is recommended the end-user, using the XML2VHDL generated XML output file(s), develops the software framework to provide the required interactions with the FPGA Firmware.