Example Generated Components

Required Libraries

Name

VHDL Library Name

From

axi4

axi4_lib

https://gitlab.stfc.ac.uk/tech-esdg/common-libraries/lib_stfc/axi4

In addition to generated files, the following VHDL files are required to be added to the final design:

axi4/src/vhdl_packages/axi4lite_pkg.vhd

axi4/src/vhdl/axi4_lite_slave_logic.vhd

axi4lite_REGISTERMAP_XML_NODENAME

Block Diagram

Attention

The axi4lite_aresetn port on the generated component is incorrectly labeled axi4lite_areset_n. This is to ensure Symbolator correctly applies an active-low marker on the port.

Port Descriptions

AXI4-Lite interface

Note

Type definitions are declared in the axi4_lib.axi4lite_pkg dependency.

Port	Direction	Type	Width	Clock Domain	Description
axi4lite_aclk	IN	std_logic	1	axi4lite_aclk	AXI4-Lite clock
axi4lite_aresetn	IN	std_logic	1	axi4lite_aclk	Must be connected. AXI4-Lite Active-Low Asynchronous Reset.
axi4lite_mosi	IN	t_axi4lite_mosi	-	axi4lite_aclk
axi4lite_miso	OUT	t_axi4lite_miso	-	axi4lite_aclk

Records to connect to/from user logic

Note

Generated types are stored in axi4lite_REGISTERMAP_XML_NODENAME_pkg.vhd in the XML_LINKED_LIB library.

Port	Direction	Type	Width	Clock Domain
axi4lite_REGISTERMAP_XML_NODENAME_in_we	IN	t_axi4lite_REGISTERMAP_XML_NODENAME_decoded	-	axi4lite_aclk
axi4lite_REGISTERMAP_XML_NODENAME_in	IN	t_axi4lite_REGISTERMAP_XML_NODENAME	-	axi4lite_aclk
axi4lite_REGISTERMAP_XML_NODENAME_out_we	OUT	t_axi4lite_REGISTERMAP_XML_NODENAME_decoded	-	axi4lite_aclk
axi4lite_REGISTERMAP_XML_NODENAME_out	OUT	t_axi4lite_REGISTERMAP_XML_NODENAME	-	axi4lite_aclk

Usage

The end-user is expected to integrate the generated VHDL files into their own designs.

Attention

This example, assumes that BUS_LINK_LIB=axi4_lib, using the XML2VHDL --bus_library "axi4_lib" argument at generation time.

Library Declarations

library axi4_lib;
use axi4_lib.axi4lite_pkg.all;
library XML_LINK_LIB;
use XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME_pkg.all;

Signal Declarations

    -- Signal declarations: ----------------------------------------------------
    signal axi4lite_REGISTERMAP_XML_NODENAME_in_we  : t_axi4lite_REGISTERMAP_XML_NODENAME_decoded;
    signal axi4lite_REGISTERMAP_XML_NODENAME_in     : t_axi4lite_REGISTERMAP_XML_NODENAME;
    signal axi4lite_REGISTERMAP_XML_NODENAME_out_we : t_axi4lite_REGISTERMAP_XML_NODENAME_decoded;
    signal axi4lite_REGISTERMAP_XML_NODENAME_out    : t_axi4lite_REGISTERMAP_XML_NODENAME;

Component Instantiation

    -- Instantiate the generated XML2VHDL component
    inst_axi4lite_REGISTERMAP_XML_NODENAME : entity XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME
        port map(
            axi4lite_aclk                            => axi4lite_aclk,
            axi4lite_aresetn                         => axi4lite_aresetn
            axi4lite_mosi                            => axi4lite_mosi,
            axi4lite_miso                            => axi4lite_miso,
            axi4lite_REGISTERMAP_XML_NODENAME_in_we  => axi4lite_REGISTERMAP_XML_NODENAME_in_we,
            axi4lite_REGISTERMAP_XML_NODENAME_in     => axi4lite_REGISTERMAP_XML_NODENAME_in,
            axi4lite_REGISTERMAP_XML_NODENAME_out_we => axi4lite_REGISTERMAP_XML_NODENAME_out_we,
            axi4lite_REGISTERMAP_XML_NODENAME_out    => axi4lite_REGISTERMAP_XML_NODENAME_out
        );

axi4lite_REGISTERMAP_XML_NODENAME_muxdemux

Block Diagram

Important

This component is generated as a dependency to axi4lite_REGISTERMAP_XML_NODENAME.vhd. It IS NOT required to be connected to the end-user design.

../_images/components-axi4lite_REGISTERMAP_XML_NODENAME_muxdemux.svg

Attention

The axi4lite_aresetn port on the generated component is incorrectly labeled axi4lite_areset_n. This is to ensure Symbolator correctly applies an active-low marker on the port.

Port Descriptions

Clocks and Resets

Port	Direction	Type	Width	Clock Domain	Description
axi4lite_aclk	IN	std_logic	1	axi4lite_aclk	AXI4-Lite clock
axi4lite_aresetn	IN	std_logic	1	axi4lite_aclk	Must be connected. AXI4-Lite Active-Low Asynchronous Reset.

IPbus - Secondary-Side

Note

Type definitions are declared in the axi4_lib.axi4lite_pkg dependency.

Port	Direction	Type	Width	Clock Domain	Description
ipb_mosi	IN	ipb_mosi	-	axi4lite_aclk
ipb_miso	OUT	ipb_miso	-	axi4lite_aclk

IPbus Array - Primary-Side

Note

Generated types are stored in axi4lite_REGISTERMAP_XML_NODENAME_pkg.vhd in the XML_LINKED_LIB library.

Port	Direction	Type	Width	Clock Domain	Description
ipb_miso_arr	IN	t_ipb_REGISTERMAP_XML_NODENAME_mosi_arr	-	axi4lite_aclk
ipb_mosi_arr	OUT	t_ipb_REGISTERMAP_XML_NODENAME_miso_arr	-	axi4lite_aclk

axi4lite_IC_XML_NODENAME_ic

Block Diagram

../_images/components-axi4lite_IC_XML_NODENAME.svg

Attention

The axi4lite_aresetn port on the generated component is incorrectly labeled axi4lite_areset_n. This is to ensure Symbolator correctly applies an active-low marker on the port.

Port Descriptions

AXI4-Lite interface

Note

Type definitions are declared in the axi4_lib.axi4lite_pkg dependency.

Port	Direction	Type	Width	Clock Domain	Description
axi4lite_aclk	IN	std_logic	1	axi4lite_aclk	AXI4-Lite clock
axi4lite_aresetn	IN	std_logic	1	axi4lite_aclk	Must be connected. AXI4-Lite Active-Low Asynchronous Reset.
axi4lite_mosi	IN	t_axi4lite_mosi	-	axi4lite_aclk
axi4lite_miso	OUT	t_axi4lite_miso	-	axi4lite_aclk

AXI4-Lite interface array

Note

Type definitions are declared in the axi4_lib.axi4lite_pkg dependency.
Helper functions to index the generated array are defined in: axi4lite_IC_XML_NODENAME_pkg in the XML_LINKED_LIB library.

Port	Direction	Type	Width	Clock Domain	Description
axi4lite_miso_arr	IN	t_axi4lite_miso_arr	-	axi4lite_aclk
axi4lite_mosi_arr	OUT	t_axi4lite_mosi_arr	-	axi4lite_aclk

Usage

The end-user is expected to integrate the generated VHDL files into their own designs.

Library declarations

library axi4_lib;
use axi4_lib.axi4lite_pkg.all;
library XML_LINK_LIB;
use XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_ic_pkg.all;
use XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.all;

Signal declarations

    -- Signal declarations: ----------------------------------------------------
    signal axi4lite_IC_XML_NODENAME_mosi_arr : t_axi4lite_mosi_arr(0 to XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.c_axi4lite_mmap_nof_slave - 1);
    signal axi4lite_IC_XML_NODENAME_miso_arr : t_axi4lite_miso_arr(0 to XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.c_axi4lite_mmap_nof_slave - 1);

Tip

To improve readability, it is recommended to create constants to declare array sizes and array indexes in the end-user host design:

    -- Constant declarations: --------------------------------------------------
    constant c_IC_XML_NODENAME_nof_secondaries : natural := XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.c_axi4lite_mmap_nof_slave;
    constant c_IC_XML_NODENAME_EXAMPLE_IC_0_id : natural := axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_0);
    constant c_IC_XML_NODENAME_EXAMPLE_IC_1_id : natural := axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_1);
    constant c_IC_XML_NODENAME_EXAMPLE_IC_2_id : natural := axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_2);
    -- Signal declarations: ----------------------------------------------------
    signal axi4lite_IC_XML_NODENAME_mosi_arr : t_axi4lite_mosi_arr(0 to c_IC_XML_NODENAME_nof_secondaries - 1);
    signal axi4lite_IC_XML_NODENAME_miso_arr : t_axi4lite_miso_arr(0 to c_IC_XML_NODENAME_nof_secondaries - 1);

Component instantiation

Referencing array IDs

Considering the following XML interconnect description and the resulting generated VHDL output:

<?xml version="1.0" encoding="ISO-8859-1"?>

<node id="IC_XML_NODENAME"  address="0x0"  hw_type="ic">
    <node id="EXAMPLE_IC_0"   address="0x0000"  link="XML_FILENAME_memory_map_output.xml"/>
    <node id="EXAMPLE_IC_1"   address="0x8000"  link="XML_FILENAME_memory_map_output.xml"/>
    <node id="EXAMPLE_IC_2"   address="0xC000"  link="XML_FILENAME_memory_map_output.xml"/>
</node>

In order to connect between other XML2VHDL generated VHDL components, generated AXI4-Lite arrays can be expanded and referenced using the IC_INDEX_NAMEs by utilising XL2VHDL VHDL helper functions:

    -- Instantiate the generated XML2VHDL Interconnect component
    inst_axi4lite_IC_XML_NODENAME_ic : entity XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_ic
    port map(
        axi4lite_aclk     => axi4lite_aclk,
        axi4lite_aresetn  => axi4lite_aresetn,
        axi4lite_mosi     => axi4lite_mosi,
        axi4lite_miso     => axi4lite_miso,
        axi4lite_miso_arr => axi4lite_IC_XML_NODENAME_mosi_arr,
        axi4lite_mosi_arr => axi4lite_IC_XML_NODENAME_miso_arr
    );

    -- Instantiate the generated XML2VHDL linked components
    inst_axi4lite_REGISTERMAP_XML_NODENAME_0 : entity XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME
        port map(
            axi4lite_aclk                            => axi4lite_aclk,
            axi4lite_aresetn                         => axi4lite_aresetn
            axi4lite_mosi                            => axi4lite_IC_XML_NODENAME_mosi_arr(axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_0)),
            axi4lite_miso                            => axi4lite_IC_XML_NODENAME_miso_arr(axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_0)),
            axi4lite_REGISTERMAP_XML_NODENAME_in_we  => axi4lite_REGISTERMAP_XML_NODENAME_0_in_we,
            axi4lite_REGISTERMAP_XML_NODENAME_in     => axi4lite_REGISTERMAP_XML_NODENAME_0_in,
            axi4lite_REGISTERMAP_XML_NODENAME_out_we => axi4lite_REGISTERMAP_XML_NODENAME_0_out_we,
            axi4lite_REGISTERMAP_XML_NODENAME_out    => axi4lite_REGISTERMAP_XML_NODENAME_0_out
        );
    
    inst_axi4lite_REGISTERMAP_XML_NODENAME_1 : entity XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME
        port map(
            axi4lite_aclk                            => axi4lite_aclk,
            axi4lite_aresetn                         => axi4lite_aresetn
            axi4lite_mosi                            => axi4lite_IC_XML_NODENAME_mosi_arr(axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_1)),
            axi4lite_miso                            => axi4lite_IC_XML_NODENAME_miso_arr(axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_1)),
            axi4lite_REGISTERMAP_XML_NODENAME_in_we  => axi4lite_REGISTERMAP_XML_NODENAME_1_in_we,
            axi4lite_REGISTERMAP_XML_NODENAME_in     => axi4lite_REGISTERMAP_XML_NODENAME_1_in,
            axi4lite_REGISTERMAP_XML_NODENAME_out_we => axi4lite_REGISTERMAP_XML_NODENAME_1_out_we,
            axi4lite_REGISTERMAP_XML_NODENAME_out    => axi4lite_REGISTERMAP_XML_NODENAME_1_out
        );

     inst_axi4lite_REGISTERMAP_XML_NODENAME_2 : entity XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME
        port map(
            axi4lite_aclk                            => axi4lite_aclk,
            axi4lite_aresetn                         => axi4lite_aresetn
            axi4lite_mosi                            => axi4lite_IC_XML_NODENAME_mosi_arr(axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_2)),
            axi4lite_miso                            => axi4lite_IC_XML_NODENAME_miso_arr(axi4lite_mmap_get_id(XML_LINKED_LIB.axi4lite_IC_XML_NODENAME_mmap_pkg.id_EXAMPLE_IC_2)),
            axi4lite_REGISTERMAP_XML_NODENAME_in_we  => axi4lite_REGISTERMAP_XML_NODENAME_2_in_we,
            axi4lite_REGISTERMAP_XML_NODENAME_in     => axi4lite_REGISTERMAP_XML_NODENAME_2_in,
            axi4lite_REGISTERMAP_XML_NODENAME_out_we => axi4lite_REGISTERMAP_XML_NODENAME_2_out_we,
            axi4lite_REGISTERMAP_XML_NODENAME_out    => axi4lite_REGISTERMAP_XML_NODENAME_2_out
        );

Tip

To improve readability, it is recommended to create constants to reference the array index identifiers:

    inst_axi4lite_REGISTERMAP_XML_NODENAME_0 : entity XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME
        port map(
            axi4lite_aclk                            => axi4lite_aclk,
            axi4lite_aresetn                         => axi4lite_aresetn
            axi4lite_mosi                            => axi4lite_IC_XML_NODENAME_mosi_arr(c_IC_XML_NODENAME_EXAMPLE_IC_0_id),
            axi4lite_miso                            => axi4lite_IC_XML_NODENAME_miso_arr(c_IC_XML_NODENAME_EXAMPLE_IC_0_id),
            axi4lite_REGISTERMAP_XML_NODENAME_in_we  => axi4lite_REGISTERMAP_XML_NODENAME_0_in_we,
            axi4lite_REGISTERMAP_XML_NODENAME_in     => axi4lite_REGISTERMAP_XML_NODENAME_0_in,
            axi4lite_REGISTERMAP_XML_NODENAME_out_we => axi4lite_REGISTERMAP_XML_NODENAME_0_out_we,
            axi4lite_REGISTERMAP_XML_NODENAME_out    => axi4lite_REGISTERMAP_XML_NODENAME_0_out
        );
    
    inst_axi4lite_REGISTERMAP_XML_NODENAME_1 : entity XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME
        port map(
            axi4lite_aclk                            => axi4lite_aclk,
            axi4lite_aresetn                         => axi4lite_aresetn
            axi4lite_mosi                            => axi4lite_IC_XML_NODENAME_mosi_arr(c_IC_XML_NODENAME_EXAMPLE_IC_1_id),
            axi4lite_miso                            => axi4lite_IC_XML_NODENAME_miso_arr(c_IC_XML_NODENAME_EXAMPLE_IC_1_id),
            axi4lite_REGISTERMAP_XML_NODENAME_in_we  => axi4lite_REGISTERMAP_XML_NODENAME_1_in_we,
            axi4lite_REGISTERMAP_XML_NODENAME_in     => axi4lite_REGISTERMAP_XML_NODENAME_1_in,
            axi4lite_REGISTERMAP_XML_NODENAME_out_we => axi4lite_REGISTERMAP_XML_NODENAME_1_out_we,
            axi4lite_REGISTERMAP_XML_NODENAME_out    => axi4lite_REGISTERMAP_XML_NODENAME_1_out
        );

     inst_axi4lite_REGISTERMAP_XML_NODENAME_2 : entity XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME
        port map(
            axi4lite_aclk                            => axi4lite_aclk,
            axi4lite_aresetn                         => axi4lite_aresetn
            axi4lite_mosi                            => axi4lite_IC_XML_NODENAME_mosi_arr(c_IC_XML_NODENAME_EXAMPLE_IC_2_id),
            axi4lite_miso                            => axi4lite_IC_XML_NODENAME_miso_arr(c_IC_XML_NODENAME_EXAMPLE_IC_2_id),
            axi4lite_REGISTERMAP_XML_NODENAME_in_we  => axi4lite_REGISTERMAP_XML_NODENAME_2_in_we,
            axi4lite_REGISTERMAP_XML_NODENAME_in     => axi4lite_REGISTERMAP_XML_NODENAME_2_in,
            axi4lite_REGISTERMAP_XML_NODENAME_out_we => axi4lite_REGISTERMAP_XML_NODENAME_2_out_we,
            axi4lite_REGISTERMAP_XML_NODENAME_out    => axi4lite_REGISTERMAP_XML_NODENAME_2_out
        );

Sometimes the end-user may want to determine the Interconnect node id= attribute value mathematically, i.e. within a VHDL generate statement. Leveraging the behaviour of Interconnect ID reference assignment it is possible to bypass the VHDL axi4lite_mmap_get_id function and use VHDL generate indexes directly.

Attention

Care should be taken when using this referencing method, as any changes to the order of Interconnect nodes in the XML input file WILL break this assignment method.

    generate_example_gen: for i in 0 to 2 generate
        inst_axi4lite_REGISTERMAP_XML_NODENAME : entity XML_LINK_LIB.axi4lite_REGISTERMAP_XML_NODENAME
            port map(
                axi4lite_aclk                            => axi4lite_aclk,
                axi4lite_aresetn                         => axi4lite_aresetn
                axi4lite_mosi                            => axi4lite_IC_XML_NODENAME_mosi_arr(i),
                axi4lite_miso                            => axi4lite_IC_XML_NODENAME_miso_arr(i),
                axi4lite_REGISTERMAP_XML_NODENAME_in_we  => axi4lite_REGISTERMAP_XML_NODENAME_in_we(i),
                axi4lite_REGISTERMAP_XML_NODENAME_in     => axi4lite_REGISTERMAP_XML_NODENAME_in(i),
                axi4lite_REGISTERMAP_XML_NODENAME_out_we => axi4lite_REGISTERMAP_XML_NODENAME_out_we(i),
                axi4lite_REGISTERMAP_XML_NODENAME_out    => axi4lite_REGISTERMAP_XML_NODENAME_out(i)
            );
    end generate generate_example_gen;