File Descriptions

Relationships

This section describes the relationship between XML input file descriptions and the resulting XML2VHDL output.

Type	XML Input File Name	Node Name	Generated XML Filename	Generated VHDL Filenames	Example
Register Map Description	XML_FILENAME.xml	REGISTERMAP_XML_NODENAME	XML_FILENAME_output.xml	axi4lite_REGISTERMAP_XML_NODENAME.vhd axi4lite_REGISTERMAP_XML_NODENAME_muxdemux.vhd axi4lite_REGISTERMAP_XML_NODENAME_pkg.vhd	<node id="REGISTERMAP_XML_NODENAME" address="0x0"> </node>
Interconnect Description	XML_FILENAME.xml IC_INDEX_NAME	IC_XML_NODENAME	XML_FILENAME_output.xml	axi4lite_IC_XML_NODENAME.vhd axi4lite_IC_XML_NODENAME_pkg.vhd axi4lite_IC_XML_NODENAME_mmap_pkg.vhd	<node id="IC_XML_NODENAME" address="0x0" hw_type="ic"> node id="IC_INDEX_NAME" address="0x0000" link="XML_FILENAME_output.xml"/> </node>

Tip

It is recommended to include the description type in the XML filename. for example by adding the following suffixes to the XML input filename:

• XML_FILENAME_memory_map.xml

• XML_FILENAME_ic_memory_map.xml

Input

XML2VHDL depends on the following input files.

See XML Descriptions for a details of the term:XML input file structure.

Input file(s) location:

Referenced using the XML2VHDL --input_folder argument.

Output

Output file(s) location:

Referenced using the XML2VHDL --relative_output_path argument.

In addition to the generated XML and VHDL output files (see Relationships). The following files are also generated:

File Type
XML files	See Relationships.
VHDL files	See Relationships and Example Generated Components.
Test-Bench files	Simulation Test-Bench files. Used to aid in interacting with the memory-map registers in hardware simulations by providing common functions, procedures and address constants of the generated registers using their XML node id= attribute. The files have the naming convention: REGISTERMAP_XML_NODENAME_tb_pkg.vhd or IC_XML_NODENAME_tb_pkg.vhd.
HTML and CSS files	These files are used together to automatically generate the register tables of the memory-maps showing their address locations and their specifications. The tables are used for legacy documentation providing the end-user a more visual and readable description of the generated output.
Other files	.hex. A compressed XML output file of the top-level, in hexadecimal form. This can used used to initialise a BRAM. .vho. A VHDL template file.