Nomenclature

To ensure consistency through-out this documentation, the following naming convention is used to describe the relationship between the XML descriptions and the generated XML and VHDL output.

Convention

attr=

Reference to a node attribute, Where attr is substituted with the actual name of the attribute.

attr="<value>"

Provides an example with node attribute value set. <value> is substituted with the example’s value.

BUS_LINK_LIB

This “linked” library is an external library which provides the VHDL definitions and resources required by the chosen Bus-side interface. See VHDL libraries.

UPPERCASE words

Indicate user-substitution for:

  • XML input filenames;

  • XML node names; and

  • XML node attribute values.

and the relationship to these UPPERCASE word substitutions in the resulting:

  • XML output filenames;

  • VHDL filenames;

  • VHDL component names;

  • VHDL package files;

  • ID references for VHDL signal array indexes; and

  • Expandible VHDL records to target register and bit-field entries.

XML_LINK_LIB

This “linked” library is used to reference the generated VHDL in the end-user host design. See VHDL libraries.

Active-low signals

Active-low signals, which may be defined in referenced materials with a line above the signal name, are suffixed with a lowercase n throughout this document.

Concepts

Node types

Type

Register

A register description, of up-to 32 bits. See Register Maps.

Register with child bit-field

A register description, of up-to 32 bits, which has additional bit-field descriptions. See Register Maps.

Interconnect

An Interconnect (IC) describes how to join other registers and interconnects. See Interconnects.

Internal Memory

A register description with attributes to describe connections to dual-port FPGA RAMs. See Internal Memory.

External Memory

See External Memory.

Sides

XML2VHDL is built around the connectivity from two interfaces. This results in the concept of sides:

  1. Bus-side. Operations which happen on the AXI4-Lite (or equivalent) interface. These are configured using the permission= node attribute; and

  2. Logic-side or Hardware-side. Operations which happen in connected user-logic, and are connected to components in the host design. These are configured using the hw_permission= and/or hw_reset= node attributes.

Host design

Host design, refers to the end-user design, to which the XML2VHDL generated output is being integrated.

VHDL libraries

Bus Library

When generating VHDL from the XML descriptions, XML2VHDL expects the output VHDL to be linked to a library. This is done using the --bus_library argument.

Important

This is an external library and NOT currently distributed with XML2VHDL. For AXI4-Lite the following (or equivalent) can be used:

XML Linked Library

When generating VHDL from the XML descriptions, XML2VHDL expects the output VHDL to be linked to a library. This is done using the --slave_library argument.

Caution

As VHDL output can be “linked” to libraries at generation time, care should be taken to include the correct generated output files in the end-user host design.

Linking

The VHDL libraries are required to be linked at XML2VHDL generation time by providing each via arguments to XML2VHDL:

xml2vhdl --bus_library "BUS_LINKED_LIB" --slave_library "XML_LINKED_LIB"