Glossary

Abbreviations

AMBA

Advanced Microcontroller Bus Architecture, an open standard on chip interconnect specification.

AMD

Advanced Micro Devices Inc. the parent company of Xilinx FPGA.

API

Application Programming Interface.

ARM

Provider of computer processor architecture, formally Acorn RISC Machine.

AXI

Advanced eXtensible Interface, an on-chip communication bus protocol which is a part of AMBA specification.

AXI4-Lite

Memory-mapped interface protocol, subset of the AMBA AXI specification.

AXI4-Stream

Point-to-point interface protocol, subset of the AMBA AXI specification.

BIN

A memory initialiation format, based on binary representation.

BRAM

Block RAM. FPGA memory resource block.

CSS

Cascading Style Sheets. Used to describe the presentation of a document written in HTML.

DED

Detector and Electronics Division. A division within TD at STFC.

DSP

Digital Signal Processing.

ESDG

Electronic System Design Group. A group within DED.

FIFO

First-In, First-Out.

FPGA

Field Programmable Gate-Array.

HDL

Hardware Description Language.

HEX

A memory initialiation format, based on hexadecimal representation.

HTML

HyperText Markup Language.

IO

Input/Output. Connections and pins to/from devices.

IP

Intellectual Property. In this context, usually refers to FPGA vendor supplied HDL to interface with FPGA resources and/or provide specific reusable functionality.

LUT

Look-Up Table. An FPGA resource, that determines the output for any-given input pattern, stored in a table.

RAM

Random Access Memory.

ROM

Read-Only Memory.

SKAO

Square Kilometre Array Observatory

STFC

Science and Technology Facilities Council.

TB

Test Bench. See Test-Bench.

TD

Technology Department. A Department within STFC.

Test-Bench

A simulation for a given HDL design.

UKRI

United Kingdom Research and Innovation.

VHDL

Very-high speed Hardware Description Language.

XML

eXtensible Markup Language.

XML2VHDL

A tool which takes XML descriptions of memory-mapped locations and converts to Synthesisable VHDL for inclusion in HDL design.

Terms

Altera

FPGA Vendor.

Bitstream

Binary file used to configure FPGA with target Firmware.

Elaboration

The 1st compilation stage of Vivado. A direct mapping of the HDL design to generic logic components such as logic gates (i.e. AND/OR); multiplexers; adders; comparators and RAM. Resulting in a non-optimised Netlist.

Firmware

Code, typically running on a FPGA device.

Git

Distributed version control system.

Github

A platform for storing and managing Git repositories.

Gitlab

A platform for storing and managing Git repositories.

Hardware

Physical elements, making up a system.

Implementation

The process of transferring the synthesised Netlist. During placement the optimised circuit is converted to target specific resource locations on the FPGA device. These locations are then connected during routing. The placement and routing consider the timing constraints of the design and tries to ensure timing is not violated on the final implemented design. Resulting in a final Netlist which can be used to generate a Bitstream.

IPbus

The IPbus protocol is a simple packet-based control protocol for reading and modifying memory-mapped resources within FPGA-based devices.

Modelsim

A tool used to simulate HDL designs.

Netlist

The resulting “circuit” from each of the FPGA compilation stages.

Non-Synthesisable

HDL which cannot be executed on target FPGA. Used for Simulation.

Poetry

A Python packaging and dependency management tool.

Primitives

The basic components on the FPGA.

Python

High-level general-purpose programming language.

Questasim

A tool used to simulate HDL designs.

Simulation

The process of testing and verifying the functionality of a design.

Software

Code, typically running on a micro-processor.

Synthesis

The process of optimising a non-optimised Netlist. This stage converts the generic logic components to target FPGA Primitives such as LUTs and BRAMs. Resulting in a synthesis Netlist.

Synthesisable

HDL which can be executed on target Hardware.

SystemVerilog

An HDL and hardware verification language.

Tcl

Scripting language, typically used by FPGA development tools.

Ultrascale+

Generational Xilinx FPGA architecture.

Verilog

A hardware description language.

Vivado

Xilinx FPGA development tool.

VUnit

A unit testing framework for HDL using Python, VHDL and SystemVerilog.

Wishbone

An open-source hardware bus architecture.

Xilinx

FPGA Vendor now owned by AMD.