Index

A

Altera AMBA AMD API

ARM AXI AXI4-Lite AXI4-Stream

B

BIN	Bitstream BRAM

C

CSS

D

DED

DSP

E

Elaboration

ESDG

F

FIFO	Firmware FPGA

G

Git	Github Gitlab

H

Hardware HDL

HEX HTML

I

Implementation IO

IP IPbus

L

LUT

M

Modelsim

N

Netlist

Non-Synthesisable

P

Poetry

Primitives Python

Q

Questasim

R

RAM

ROM

S

Simulation SKAO Software

STFC Synthesis Synthesisable SystemVerilog

T

TB Tcl

TD Test-Bench

U

UKRI	Ultrascale+

V

Verilog VHDL

Vivado VUnit

W

Wishbone

X

Xilinx XML

XML2VHDL Xml2Vhdl (class in xml2vhdl) Xml2VhdlGenerate (class in xml2vhdl)