XML2VHDL (v0.8.1)

XML2VHDL is a Python based framework to describe complex memory-mapped address spaces using one or more XML input files. These can then be used to generate VHDL components and support packages for the end-user to integrate into their own Firmware host designs.

The aim of XML2VHDL is to bridge Firmware and Control Software consistently. This can be achieved by including XML2VHDL in the build-chain for both FPGA Firmware and the Software development flow.

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Features

XML2VHDL has the following features:

  • Supports Wishbone and AXI4-Lite based interfaces.

  • Provides a hierarchical tree structure, promoting XML file reuse and interoperability between VHDL libraries.

  • Generates XML output files, which can be used by other tools to process and manage memory-mapped address spaces (i.e. linking to Python support modules and/or generating documentation).

  • Generates VHDL components.

  • Generates VHDL package files defining array and record structures, allowing the end-user to reference registers and bit-fields by name - simplifying design entry.

  • Generates HEX files containing the XML output, which can be used to initiate FPGA BRAM - allowing for systems to become self describing.

Important

Whist XML2VHDL provides all the features listed above, the end-user is still required to manually insert the generated VHDL into their own Firmware designs.

Hierarchical Tree Structure

XML2VHDL is used to describe the address-space of both simple and complex end-user host designs. To achieve this, a hierarchical design methodology is employed. This allows the end-user to describe a top-level XML description of the host design. By using an Interconnect description to link host design specific elements and/or pre-existing XML descriptions of re-usable components via external VHDL libraries. The resulting XML descriptions have the following structure:

  • A top-level, providing the complete, global address-space of the end-user host design; where each element has:

  • A first-level, defining the different functional memory-mapped components used throughout the host design; where each element has:

  • Second-level descriptions representing registers and/or addressable memories; where:

  • Optionally, a third-level describes registers with child bit-fields broken down.

Note

Usually, the top-level and first-level descriptions are defined using Interconnects, The second-level and third-level are defined in the same register XML description.

When generating output products, XML2VHDL processes the XML input files using a bottom to top approach. This means that every second-level/third-level description is processed and has its own flattened XML output file. These output files are then applied to the hierarchical level(s) above, which is again flattened into separate XML output files at each hierarchical level. This process is repeated until the top-level, global address-space has been generated. The final flattened XML output file represents the complete address-map of the end-user host design.

Throughout this (recursive) process, the base-address from the lower-level descriptions will propagate towards the top-level description by applying them as address offsets to high-level descriptions. This results in the absolute addresses for each memory-mapped location being described in the XML output file at each hierarchical level.

The advantage to generating, and using, XML output file descriptions at each of these hierarchical levels is that corresponding control/monitoring software can be developed and maintained at each level and provided for each functional memory-mapped component used in the end-user host design.

Collaborators

XML2VHDL was originally developed by collaborators from the University of Oxford and STFC | TD | DED | ESDG based at Rutherford Appleton Laboratory.