SKA PST DSP Architecture

The Digital Signal Processing (DSP) component of the Pulsar Timing (PST) product is responsible for performing the digital signal processing of the channelised voltages in the tied-array beam data generated by the Correlator Beam Former (CBF) producing reduced data products that will be transmitted to the Science Data Processor (SDP) for subsequent secondary analysis.

The PST DSP component is configured, controlled, and monitored by via a gRPC interface with PST LMC.

DSP will consist of signal processing functionality that will be incrementally released throughout the array released schedule and will be delivered in the following order:

1. AA0.5 Disk Voltage Recorder

2. AA1 Flow Through Mode

3. AA2 Detected Filterbank Mode (limited channelisation)

4. AA3 Pulsar Timing Mode (limited channelisation)

5. AA4 Detected Filterbank and Pulsar Timing Modes (complete)

• AA0.5 Voltage Recorder
  • Decomposition
  • Data Product Structure
• AA1.0 Flow Through Mode
  • Decomposition
  • Data Product Structure

State Model

PST DSP applications interface with the shared memory ring buffer as depicted in the following sequence diagram.

Sequence diagram showing interaction with the ring buffer