TpmPatternGenerator

Overview

This plugin is responsible for managing the TPM FPGA firmware pattern generators. These are used during validation of the FPGA firmware and DAQ to substitue simple patterns into the data stream at the following points: * ADC output (JESD bus output) * Channelizer output * Tile beamformer output

Python Class & Methods Index

class ska_low_sps_tpm_api.plugins.pattern_generator.TpmPatternGenerator(board, logger=None, **kwargs)

Pattern generator

__init__(board, logger=None, **kwargs)

TpmPatternGenerator initialiser.

Parameters:

board – Pointer to board instance

channelize_pattern(pattern)

Change the frequency channel order to match che channelizer output.

Parameters:

pattern – pattern buffer, frequency channel in increasing order

check_stage(stage)

clean_up()

Perform cleanup.

Returns:

Success

clear_signal_adder(stage)

Clear signal adder. Set to zero the signal adder of each signal.

Parameters:

stage – stage where write clear to signal adders

disable_ramp(stage)

Disable ramp for a given stage.

enable_ramp(stage, polarisation=0, ramp='ramp1')

Enable ramp for a given stage.

Parameters:

• stage – the stage to set the ramp

• polarisation – the polarisation to apply the ramp for.

• ramp – must be (ramp1 or ramp2). (note: ramp2 = ramp1 + 1234)

Raises:

ValueError – when ramp is not in (ramp1, ramp2)

Return type:

None

get_pattern(stage='channel')

Read pattern from FPGA internal BRAM buffer.

Parameters:

stage – stage where write the pattern: jesd, channel or beamf

initialise(nof_inputs_per_fpga=16)

Initialise Pattern Generator with default incremental pattern

set_pattern(buff, stage='channel')

Write pattern in FPGA internal BRAM buffer.

Parameters:

• buff – pattern buffer, each element represents an output value

• stage – stage where write the pattern: jesd, channel or beamf

set_random_pattern(stage='channel', seed=0)

Write a randmon pattern in FPGA internal BRAM buffer.

Parameters:

• stage – stage where write the pattern: jesd, channel or beamf

• seed – seed for random number generator generator

set_shift(shift, stage)

Set the bit shift. If used in ‘beamf’ stage, the value is overridden to 4.

Parameters:

• stage – stage where to set bit shift

• shift – bit shift (divides the pattern by 2^shift)

set_signal_adder(adder_list, stage)

Set signal adder. For each signal its pattern is constructed by adding a value to the pattern of input 0.

Parameters:

• adder_list – list of 64 adder (one adder per each signal and muxed value = 16*4)

• stage – stage where write the pattern: jesd, channel or beamf

set_zero(zero, stage)

Set mask on specific antenna/polarisation.

Parameters:

• stage – stage where to set mask.

• zero – An integer (0-65535) used as a mask to disable the pattern on specific antennas and polarizations. The same mask is applied to both FPGAs, supporting up to 8 antennas and 2 polarizations. The default value is 0.

start_pattern(stage)

Start pattern.

Parameters:

stage – stage where start the pattern: jesd, channel or beamf

status_check()

Abstract method where all status checks should be performed.

Returns:

Firmware status

stop_pattern(stage)

Stop pattern.

Parameters:

stage – stage where stop the pattern: jesd, channel or beamf