TpmJesd

Overview

This plugin is responsible for managing the TPM FPGA firmware JESD204B bus used for the transmission of data from ADCs to FPGA.

Python Class & Methods Index

class ska_low_sps_tpm_api.plugins.jesd.TpmJesd(board, logger=None, **kwargs)[source]

TpmJesd plugin

__init__(board, logger=None, **kwargs)[source]

TpmJesd initialiser.

Parameters:: board – Pointer to board instance

check_link_error_counter()[source]

check_link_error_status()[source]

check_qpll_lock_loss_counter(show_result=True)[source]

check_qpll_lock_status()[source]

check_resync_counter(show_result=True)[source]: Resync count is implemented in firmware to increment on each rising edge of the sync signal. Sync signal is the AND of both JESD cores.

check_sync_status()[source]

clean_up()[source]

Perform cleanup.

Returns:: Success

clear_error_counters()[source]

disable_all_lanes()[source]

enable_all_lanes()[source]

initialise()[source]: Initialise TpmJesd

jesd_core_check()[source]

jesd_core_restart()[source]

jesd_core_start(single_lane=False, octects_per_frame=None, lane_in_use=255, disable_core=False)[source]: !@brief This function performs the FPGA internal JESD core configuration and initialization procedure as implemented in ADI demo.

jesd_lane_zero(lanes)[source]

status_check()[source]

Perform status check.

Returns:: Status