Tile Interface

The tile and station Python classes were originally created to the enable control of the AAVS (Aperture Array Verification System) prototype station deployments, AAVS1, AAVS2 and AAVS3. With the aim of demonstrating and to de-risking the development of the signal processing chain.

The tile object and its methods now provide monitoring and control API for the Tile Processing Modules to the SKA-Low telescopes Monitor Control & Calibration System (MCCS).

As there are many tile methods that providing board status “health” reporting, these have been separated into a Tile Health Monitor Mixin Class, must be inherited by the Tile Python class.

Tile

Software representation of the Tile Processing Module. Monitoring and control of hardware and firmware functions.

class ska_low_sps_tpm_api.tile.Tile(ip='10.0.10.2', port=10000, sampling_rate=800000000.0, logger=None, tpm_version=None)

Tile hardware interface library.

__getattr__(name)

Handler for any requested attribute not found in the usual way; tries to return the corresponding attribute of the connected TPM.

Parameters:

name (str) – name of the requested attribute

Raises:

AttributeError – if neither this class nor the TPM has the named attribute.

Returns:

the requested attribute

Return type:

object

__getitem__(key)

Read a register using indexing syntax: value=tile['registername'].

Parameters:

key (str) – register address, symbolic or numeric

Returns:

indexed register content

Return type:

int

__init__(ip='10.0.10.2', port=10000, sampling_rate=800000000.0, logger=None, tpm_version=None)

Iniitalise a new Tile instance.

Parameters:

• ip (str) – IP address of the hardware

• port (int) – UCP Port address of the hardware port

• sampling_rate (float) – ADC sampling rate

• logger (logging.Logger) – the logger to be used by this Command. If not provided, then a default module logger will be used.

• tpm_version (str) – target TPM hardware version

__setitem__(key, value)

Set a register to a value.

Parameters:

• key (str) – register address, symbolic or numeric

• value (int) – value to be written into register

__str__()

Produces list of tile information

Returns:

Information string

Return type:

str

property active_40g_port

property adc_fullscale_voltage

Get the input full-scale voltages configured in all 16 ADCs.

Returns:

List of input full-scale voltages in Volts

Return type:

list(float)

beamformer_is_running(mask=None, beam=None, channel_groups=None)

Check if station beamformer is running.

Channels to be checked can be specified (in rder of priority) as

Parameters:

• mask (int) – Bitmask of the channels to check

• beam (int | None) – Beam number to check. Computes mask using beam table

• channel_groups (list | None) – Groups of 8 channels each (0 = channels 0-7)

Returns:

beamformer running status

Return type:

bool

property broadband_rfi_factor

Gets the RFI factor for broadband RFI detection Note: Only the RFI factor of FPGA1 is read, since the same value is loaded into all FPGAs.

Returns:

rfi_factor: the sensitivity value for the RFI detection

Return type:

float

static calculate_delay(current_delay, current_tc, target, margin)

Calculate delay for PPS pulse.

Parameters:

• current_delay (int) – Current delay

• current_tc (int) – Current phase register terminal count

• target (int) – target delay

• margin (int) – marging, target +-margin

Returns:

Modified phase register terminal count

Return type:

int

Raises:

ValueError – Unable to calculate delay

check_40g_test_result()

Check 40G embedded test result.

check_arp_table(timeout=30.0)

Check that ARP table has been resolved for all used cores. See report_sdn_routing() for details of each specific ARP table entry. The procedure checks that all populated ARP entries have been resolved. If the QSFP has been disabled or link is not detected up, the check is skipped.

Parameters:

timeout (float) – Timeout in seconds

Returns:

ARP table status

Return type:

bool

check_communication()

Checks status of connection to TPM CPLD and FPGAs. Returns dictionary of connection status. .. rubric:: Examples

• OK Status: {'CPLD': True, 'FPGA0': True, 'FPGA1': True}

• TPM ON, FPGAs not programmed or TPM overtemperature self shutdown: {'CPLD': True, 'FPGA0': False, 'FPGA1': False}

• TPM OFF or Network Issue: {'CPLD': False, 'FPGA0': False, 'FPGA1': False}

Non-destructive version of tile tpm_communication_check

Returns:

Dictionary of CPLD & FPGA status

Return type:

dict of bool

check_dsp_latency(fpga_id=None)

Returns DSP latency in ms

The DSP latency is calculated by measuring the difference between the SPEAD transmission timestamp in the station beamformer and the ADC sampling timestamp for the same packet.

NOTE: if this is run on on tile which is not the final one a latency of zero will be returned

Parameters:

fpga_id (int) – Specify which FPGA, 0,1, or None for both FPGAs

Returns:

dictionary or float of DSP latency in ms

Return type:

dict(float) | float

check_dsp_output_spead_timestamp(fpga_id=None)

Returns current station beam output SPEAD packet timestamp in UTC

Parameters:

fpga_id (int) – Specify which FPGA, 0,1, or None for both FPGAs

Returns:

dictionary or integer of output spead timestamp in UTC

Return type:

integer

check_fpga_synchronization()

Checks various synchronization parameters.

Output in the log

Returns:

OK status

Return type:

bool

check_pending_data_requests()

Checks whether there are any pending data requests.

Returns:

true if pending requests are present

Return type:

bool

check_pll_locked()

Check if PLL is locked to external reference clock.

Returns:

True if PLL is locked to external reference clock.

check_pll_reference()

Check PLL lock reference.

NOTE: If the TPM is fitted in a subrack, the external reference will always be present and provided from the subrack. In this case, the subrack will also need to be monitored to determine if it is using an internal or external reference clock.

Returns:

“external” if PLL is locked to external reference clock. “internal” if PLL is locked to interfal reference clock. None if PLL is not locked.

check_synchronised_data_operation(requested_timestamp=None)

Check if synchronise data operations between FPGAs is successful.

Parameters:

requested_timestamp (int) – Timestamp written into FPGA timestamp request register. If None it will be read from the FPGA register.

Returns:

Operation success

Return type:

bool

check_valid_timestamp_request(daq_mode, fpga_id=None)

Check valid timestamp request for various modes. modes supported: raw_adc, channelizer and beamformer.

Parameters:

• daq_mode (str) – string used to select which Flag register of the LMC to read

• fpga_id (int) – FPGA_ID, 0 or 1. Default None will select both FPGAs

Returns:

boolean to indicate if the timestamp request is valid or not

Return type:

bool

clear_adc_overrange(adcs=range(0, 16))

Clear the overrange status bits of the 2 channels of the specified ADCs

Parameters:

adcs (list(int)) – List of ADC IDs to be configured

clear_broadband_rfi()

Clear all RFI counts registers.

clear_lmc_data_request()

Clear LMC data request register. This would be normally self-cleared by the firmware, however in case of failed synchronisation, the firmware will not clear the register. In that case the request register can be cleared by software to allow the next data request to be executed successfully.

clear_timestamp_invalid_flag_register(daq_mode=None, fpga_id=None)

Clear invalid timestamp request register for selected fpga and for selected LMC request mode . Default clears all registers for all modes.

Parameters:

• daq_mode (str) – string used to select which Flag register of the LMC to read

• fpga_id (int) – FPGA_ID, 0 or 1. Default None will select both FPGAs

Raises:

LibraryError – Invalid DAQ mode specified

compute_calibration_coefficients()

Compute the calibration coefficients and load them in the hardware.

configure_40g_core(core_id=0, arp_table_entry=0, src_mac=None, src_ip=None, src_port=None, dst_ip=None, dst_port=None, rx_port_filter=None, netmask=None, gateway_ip=None)

Configure a 40G core.

Parameters:

• core_id (int) – 40G core ID

• arp_table_entry (int) – ARP table entry ID

• src_mac (int) – Source MAC address

• src_ip (int | str) – Source IP address

• dst_ip (int | str) – Destination IP

• src_port (int) – Source port

• dst_port (int) – Destination port

• rx_port_filter (int) – Filter for incoming packets

• netmask (int | str) – Netmask

• gateway_ip (int | str) – Gateway IP

configure_active_40g_ports(configuration)

Configure which of the two 40G QSFP ports is used. Options are:

• Port 1 Only: “port1-only” (lower TPM 40G port, labeled P1 on newer subracks)

• Port 2 Only: “port2-only” (upper TPM 40G port, labeled P2 on newer subracks)

• Both Port 1 and Port 2: “both-ports”

• Neither Port 1 or Port 2: None

Parameters:

configuration (str | None) – port1-only, port2-only, both-ports, None

configure_integrated_beam_data(integration_time=0.5, first_channel=0, last_channel=191)

Configure and start continuous integrated beam data.

Parameters:

• integration_time (float, optional) – integration time in seconds, defaults to 0.5

• first_channel (int, optional) – first channel

• last_channel (int, optional) – last channel

configure_integrated_channel_data(integration_time=0.5, first_channel=0, last_channel=511)

Configure and start continuous integrated channel data.

Parameters:

• integration_time (float, optional) – integration time in seconds, defaults to 0.5

• first_channel (int, optional) – first channel

• last_channel (int, optional) – last channel

configure_ramp_pattern(stage, polarisation, ramp)

Configure a ramp pattern.

Parameters:

• stage (str) – one of (“jesd”, “channel”, “beamf”, “all”)

• polarisation (int) – one of (0, 1, -1). select -1 for “all” polariations

• ramp (str) – (“ramp1”, “ramp2”, “all”)

Return type:

None

connect(initialise=False, load_plugin=True, enable_ada=False, enable_adc=True, dsp_core=True, adc_mono_channel_14_bit=False, adc_mono_channel_sel=0, adc_fullscale_voltage=1.59)

Connect to the hardware and loads initial configuration.

Parameters:

• initialise (bool) – Initialises the TPM object

• load_plugin (bool) – loads software plugins

• enable_ada (bool) – Enable ADC amplifier (usually not present)

• enable_adc (bool) – Enable ADC

• dsp_core (bool) – Enable loading of DSP core plugins

• adc_mono_channel_14_bit (bool) – Enable ADC mono channel 14bit mode

• adc_mono_channel_sel (int) – Select channel in mono channel mode (0=A, 1=B)

• adc_fullscale_voltage (float) – ADC input full-scale voltage

current_station_beamformer_frame()

Query time of packets at station beamformer input.

Returns:

current frame, in units of 256 ADC frames (276,48 us)

Return type:

int

current_tile_beamformer_frame()

Query time of packets at tile beamformer input.

Returns:

current frame, in units of 256 ADC frames (276,48 us)

Return type:

int

define_channel_table(region_array, fpga_id=None)

Set frequency regions.

Regions are defined in a 2-d array, for a maximum of 16 regions. Each element in the array defines a region, with the form: [start_ch, nof_ch, beam_index, <optional> subarray_id, subarray_logical_ch, aperture_id, substation_id]

• 0: start_ch: region starting channel (currently must be a multiple of 2, LS bit discarded).

• 1: nof_ch: size of the region: must be multiple of 8 chans.

• 2: beam_index: subarray beam used for this region, range [0:48).

• 3: subarray_id: ID of the subarray [1:48].

• 4: subarray_logical_channel: Logical channel in the subarray it is the same for all (sub)stations in the subarray. Defaults to station logical channel.

• 5: subarray_beam_id: ID of the subarray beam. Defaults to beam index.

• 6: substation_ID: ID of the substation. Defaults to 0 (no substation).

• 7: aperture_id: ID of the aperture (station*100+substation?).

Note: this is a wrapper method of 'boards.tpm.station_beamf.define_channel_table'

Total number of channels must be <= 384.

The routine computes the arrays beam_index, region_off, region_sel, and the total number of channels nof_chans, and programs it in the hardware. Optional parameters are placeholders for firmware supporting more than 1 subarray. Current firmware supports only one subarray and substation, so corresponding IDs must be the same in each row

Parameters:

• fpga_id (2d list of int) – the id of the fpga we want to define the channel table for. if None both are configured.

• region_array (List[List[int]]) – bidimensional array, one row for each spectral region, 3 or 8 items long

Returns:

True if OK

Return type:

bool

define_spead_header(station_id, subarray_id, nof_antennas, ref_epoch=-1, start_time=0, ska_spead_header_format=False)

Define SPEAD header for last tile.

All parameters are specified by the LMC.

Parameters:

• station_id (int) – Station ID

• subarray_id (int) – Subarray ID

• nof_antennas (int) – Number of antennas in the station

• ref_epoch (int) – Unix time of epoch. -1 uses value defined in set_epoch

• start_time – start time (TODO describe better)

• ska_spead_header_format (bool) – Sets the CSP spead header to the version specified in ICD ECP-230134

Returns:

True if parameters OK, False for error

Return type:

bool

disable_adc_test_mode(adcs=range(0, 16))

Disable ADC Test Mode.

Parameters:

adcs (list(int)) – List of ADC IDs to be configured

disable_all_adcs()

Disable all lanes on each FPGA.

disable_broadband_rfi_blanking(antennas=range(0, 16))

Disables RFI detection on set antennas.

Parameters:

antennas (list(int)) – list antennas where RFI will be disabled

disable_station_beam_flagging(fpga_id=None)

NOTE: this only affects the last tile in the station beam chain. This disables the transmission of incomplete frames, if a frame is not complete, the entire frame will be dropped. No flagging will occur and this will appear as packet loss to CSP.

disconnect()

Close connections.

enable_adc_test_mode(pattern_type, adcs=range(0, 16))

Configure ADC Test Mode.

The AD9695 ADC supports the following test modes:

• midscale: A constant output of the ADC midscale value.

• full-scale-positive: A constant output of the ADC positive maximum value.

• full-scale-negative: A constant output of the ADC negative maximum value.

• checkerboard: A repeating pattern of alternating 1’s and 0’s. Words alternate between 0x2AAA and 0x1555.

• pn-long: A PN23 (Pseudo-Random Noise) sequence.

• pn-short: A PN9 (Pseudo-Random Noise) sequence.

• one-zero-alternate: A repeating pattern of alternating 1’s and 0’s. Words alternate between 0x0000 and 0x3FFF.

• fixed: A repeating pattern of four user provided values. These can be specified with set_adc_test_pattern below.

• ramp A linear ramp pattern increasing from 0x000 to 0x3FFF then repeating.

For more details see the Analog Devices AD9695 Data Sheet

Parameters:

• pattern_type (str) – Name of test mode to be enabled

• adcs (list(int)) – List of ADC IDs to be configured

enable_all_adcs()

Enable all lanes on each FPGA.

enable_broadband_rfi_blanking(antennas=range(0, 16))

Enables broadband rfi blanking on set antennas.

Parameters:

antennas (list(int)) – list antennas where broadband RFI blanking will be enabled

enable_station_beam_flagging(fpga_id=None)

NOTE: this only affects the last tile in the station beam chain. This enables the transmission of incomplete frames, any packets in the frame that are missing will be substituted for the reserved value (flagged).

equalize_preadu_gain(required_rms=20)

Equalize the preadu gain to get target RMS.

Parameters:

required_rms (int) – Target RMS

erase_fpgas()

Erase FPGA configuration memory.

f2f_aurora_test_check()

Get test results for Aurora f2f link Tests printed on stdout.

f2f_aurora_test_start()

Start test on Aurora f2f link.

f2f_aurora_test_stop()

Stop test on Aurora f2f link.

find_register(register_name='', display=False, info=False)

Return register information from a provided search string.

Note: this is a wrapper method of 'boards.tpm.find_register'

Parameters:

• register_name (str) – Regular expression to search against.

• display (bool) – True to output result to console.

• info (bool) – print a message with additional information if True.

Returns:

List of found registers.

Return type:

list

get_40g_core_configuration(core_id, arp_table_entry=0)

Get the configuration for a 40g core.

Parameters:

• core_id (int) – Core ID

• arp_table_entry (int) – ARP table entry to use

Returns:

core configuration

Return type:

dict

get_40g_packet_counts()

Get 40G packet counts.

The return value depends on how many 40G cores are active. Typically, only one core is active.

Example:

# 0 cores active
{}

# 1 core active
{
    'FPGA0': {
        'rx_received': 2921,
        'rx_forwarded': 0,
        'tx_transmitted': 6973024
    }
}

# 2 cores active
{
    'FPGA0': {
        'rx_received': 3881,
        'rx_forwarded': 0,
        'tx_transmitted': 7321460
    },
    'FPGA1': {
        'rx_received': 1,
        'rx_forwarded': 0,
        'tx_transmitted': 3122
    }
}

Returns:

Packet counts per active 40G core. Returns an empty dictionary if no 40G cores are active.

Return type:

dict

get_adc_rms(sync=False)

Get ADC power, immediate.

Parameters:

sync (bool) – Synchronise RMS read

Returns:

ADC RMS power

Return type:

list(float)

get_arp_table()

Check that ARP table has been populated in for all used cores. Returns a dictionary with an entry for each core present in the firmware Each entry contains a list of the ARP table IDs which have been resolved by the ARP state machine.

Returns:

list of populated core ids and arp table entries

Return type:

dict(list)

get_beamformer_regions()

Get frequency regions. Read the beamformer regions in the channelizer, with all the parameters for each region. Note: Only FPGA1 tables are read because the same region_array is written to FPGA2. Regions are defined in a 2-d array, for a maximum of 16 (48) regions. Each element in the array defines a region, with the form [start_ch, nof_ch, beam_index]

• start_ch: region starting channel (currently must be a multiple of 2, LS bit discarded).

• nof_ch: size of the region: must be multiple of 8 chans.

• beam_index: beam used for this region, range [0:8).

• subarray_id: ID of the subarray [1:48].

• subarray_logical_channel: Logical channel in the subarray it is the same for all (sub)stations in the subarray. Defaults to station logical channel.

• subarray_beam_id: ID of the subarray beam. Defaults to beam index.

• substation_ID: ID of the substation. Defaults to 0 (no substation).

• aperture_id: ID of the aperture (station*100+substation?). Defaults to antenna ID = 1, substation ID.

Returns:

Bidimensional array of regions

Return type:

list(list(int))

get_beamformer_table(fpga_id=0)

Returns a table with the following entries for each 8-channel block:

• 0: start physical channel (64-440).

• 1: beam_index: subarray beam used for this region, range [0:48).

• 2: subarray_id: ID of the subarray [1:48]. Here is the same for all channels.

• 3: subarray_logical_channel: Logical channel in the subarray. Here equal to the station logical channel.

• 4: subarray_beam_id: ID of the subarray beam.

• 5: substation_id: ID of the substation.

• 6: aperture_id: ID of the aperture (station*100+substation?).

Parameters:

fpga_id (int) – A parameter to specify what fpga we want to return the beamformer table for. (Default fpga_id = 0)

Note: this is a wrapper method of 'boards.tpm.station_beamf.get_channel_table'

Returns:

Nx7 table with one row every 8 channels

Return type:

Nx7 list

get_channeliser_truncation()

Get channeliser truncation scale for the whole tile. Note: Only the FPGA1 table is read because the same value is written to FPGA2.

Returns:

List of Channeliser truncation rescale data table contents

Return type:

list

get_csp_rounding()

Reads the csp rounding register from hardware. Note, only checks first FPGA as they should match

Returns:

CSP rounding value stored in the register of FPGA 1

Return type:

int

get_ddr_if_stat(key, fpga_id=0)

DDR interface status.

The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components.

Each FPGA has its own independent DDR4 SDRAM.

Parameters:

• key (str) – ddr_if register

• fpga_id (int) – FPGA 0 or FPGA 1

Returns:

ddr_if register contents

Return type:

int

get_firmware_list()

Get information for loaded firmware.

Returns:

Firmware information dictionary for each loaded firmware

Return type:

list(dict)

get_fpga0_temperature()

Get FPGA0 temperature.

Returns:

FPGA0 temperature

Return type:

float

get_fpga1_temperature()

Get FPGA1 temperature.

Returns:

FPGA0 temperature

Return type:

float

get_fpga_time(device)

Return time from FPGA.

Parameters:

device (Device) – FPGA to get time from

Returns:

Internal time for FPGA

Return type:

int

Raises:

LibraryError – Invalid value for device

get_fpga_timestamp(device=Device.FPGA_1)

Current FPGA timestamp. This returned value is the time since sync time expressed in units of 0.27648 ms.

This time scale used for any synchronous operation in the TPM, and the reason why the tile has to be reinitialised at most every 13.7 days (2^32 timestamp units).

Parameters:

device (Device) – FPGA to read timestamp from

Returns:

PPS time

Return type:

int

Raises:

LibraryError – Invalid value for device

get_intTime()

Gets the current integration time in seconds. This is the time period over which the ADC power is averaged to get the RMS. Note: Only the integration time of FPGA1 is read, since the same value is loaded into all FPGAs.

Returns:

integration time in seconds

Return type:

float

get_ip()

Get tile IP.

Returns:

tile IP address

Return type:

str

get_phase_terminal_count()

Get PPS phase terminal count.

Returns:

PPS phase terminal count

Return type:

int

get_pointing_delay(beam_index)

This method retrives the given input delay and delay rate for all 16 antennas from both FPGAs for a given beam_index. The beam_index is specified from (current range 0-47)

Parameters:

beam_index (int) – hardware station beam to read. Range 0-47

Returns:

A multi dimensional list containing the input delay and delay rates for all all 16 antennas from FPGA 1 and FPGA2 for a given beam_index

Return type:

read_beam_antenna_delay : list(list(list(float, float) * 8), list(list(float, float) * 8))

get_pps_delay(enable_correction=True)

Get delay between PPS and 10 MHz clock.

Parameters:

enable_correction (bool) – enable PPS delay correction using value configured in the FPGA1

Returns:

delay between PPS and 10 MHz clock in 200 MHz cycles

Return type:

int

get_preadu_levels()

Get preADU attenuation levels.

Returns:

Attenuation levels corresponding to each ADC channel, in dB.

Return type:

list of float

get_rx_adc_rms()

Get ADC power.

Returns:

ADC RMS power

Return type:

list(float)

get_station_id()

Get station ID

Returns:

station ID programmed in HW

Return type:

int

get_temperature()

TPM board temperature. This is the temperature as reported by a PCB temperature sensor located near the ADCs. Measurement is a float in °C.

Returns:

board temperature

Return type:

float

get_tile_id()

Get tile ID.

Returns:

programmed tile id

Return type:

int

property has_preadu

Check if tile has preADUs fitted. Gets preadu attribute “is_present” for each preADU.

Returns:

True if a preADU is present, else False

Return type:

list(bool)

property independent_fortyg_lmc_dest_support

Check if Independent 40GbE destinations for different data products is supported.

Returns:

True if firmware supports independent 40GbE destinations per data product.

Return type:

bool

property info

initialise(station_id=0, tile_id=0, lmc_use_40g=False, lmc_dst_ip=None, lmc_dst_port=4660, lmc_integrated_use_40g=False, lmc_integrated_dst_ip=None, lmc_integrated_dst_port=4660, src_ip_fpga1=None, src_ip_fpga2=None, dst_ip_fpga1=None, dst_ip_fpga2=None, src_port=4661, dst_port=4660, netmask_40g=None, gateway_ip_40g=None, active_40g_ports_setting='port1-only', enable_adc=True, enable_ada=False, use_internal_pps=False, pps_delay=0, time_delays=0, pps_period=1, is_first_tile=False, is_last_tile=False, qsfp_detection='auto', adc_mono_channel_14_bit=False, adc_mono_channel_sel=0, adc_fullscale_voltage=1.59, global_start_time=None)

Connect and initialise.

Parameters:

• enable_ada (bool) – enable adc amplifier, Not present in most TPM versions

• enable_adc (bool) – Enable ADC

• use_internal_pps (bool) – use internal PPS generator synchronised across FPGAs

• qsfp_detection (str) – “auto” detects QSFP cables automatically, “qsfp1”, force QSFP1 cable detected, QSFP2 cable not detected “qsfp2”, force QSFP1 cable not detected, QSFP2 cable detected “all”, force QSFP1 and QSFP2 cable detected “none”, force no cable not detected

• adc_mono_channel_14_bit (bool) – Enable ADC mono channel 14bit mode

• adc_mono_channel_sel (int) – Select channel in mono channel mode (0=A, 1=B)

• global_start_time (int) – Sets internal TPM start time, used to synchronize to other TPM’s

• adc_fullscale_voltage (float) – ADC input full-scale voltage

initialise_beamformer(start_channel, nof_channels, beam_index=0)

Initialise tile and station beamformers for a simple single beam configuration.

Parameters:

• start_channel (int) – Initial channel, must be even

• nof_channels (int) – Number of beamformed spectral channels

is_programmed()

Check whether the TPM is connected and programmed.

Returns:

If the TPM is programmed

Return type:

bool

is_qsfp_module_plugged(qsfp_id=0)

Initialise firmware components.

Returns:

True when cable is detected

Return type:

bool

is_station_beam_flagging_enabled(fpga_id=None)

Get the station beam flag state for each FPGA.

Returns:

station beam flag values as list of bool values

Return type:

list

load_calibration_coefficients(antenna, calibration_coefficients)

Loads calibration coefficients.

calibration_coefficients is a bi-dimensional complex array of the form calibration_coefficients[channel, polarization], with each element representing a normalized coefficient, with (1.0, 0.0) the normal, expected response for an ideal antenna.

channel is the index specifying the channels at the beamformer output, i.e. considering only those channels actually processed and beam assignments. The polarization index ranges from 0 to 3.

• 0: X polarization direct element

• 1: X->Y polarization cross element

• 2: Y->X polarization cross element

• 3: Y polarization direct element

The calibration coefficients may include any rotation matrix (e.g. the parallitic angle), but do not include the geometric delay.

Parameters:

• antenna (int) – Antenna number (0-15)

• calibration_coefficients (list(float)) – Calibration coefficient array

load_calibration_coefficients_for_channels(first_channel, calibration_coefficients)

Loads calibration coefficients for all antennas and specific channels.

calibration_coefficients is a tri-dimensional complex array of the form calibration_coefficients[channel, antennam, polarization], with each element representing a normalized coefficient, with (1.0, 0.0) the normal, expected response for an ideal antenna.

channel is the index specifying the channels at the beamformer output, i.e. considering only those channels actually processed and beam assignments. First channel is specified in the parameter, the number of channels is determined by the array shape.

antenna is the antenna index, ranging 0 to 15.

The polarization index ranges from 0 to 3.

• 0: X polarization direct element

• 1: X->Y polarization cross element

• 2: Y->X polarization cross element

• 3: Y polarization direct element

The calibration coefficients may include any rotation matrix (e.g. the parallitic angle), but do not include the geometric delay.

Parameters:

• first_channel – Antenna number (0-15)

• calibration_coefficients (numpy.array([-1, 16, 4], complex)) – Calibration coefficient array

load_pointing_delay(load_time=0, load_delay=64)

Delay is updated inside the delay engine at the time specified. If load_time = 0 load immediately applying a delay defined by load_delay

Parameters:

• load_time (int) – time (in ADC frames/256) for delay update

• load_delay (int) – delay in (in ADC frames/256) to apply when load_time == 0

load_scan_id(beam=None, channel_groups=None, scan_id=0)

Set the scan ID for a given beam or set of channels, default for all.

Specification may be any of the following, in order of priority:

Parameters:

• beam (int | None) – Beam number to start. Computes the mask using beam table

• channel_groups (list | None) – list of channel groups, in range 0:48. group 0 for channels 0-7, to group 47 for channels 380-383

• scan_id (int) – the new scan ID to set

max_broadband_rfi(antennas=range(0, 16))

The maximum number of ADC frames containing broadband RFI across all antennas.

A count is maintained per dual polarisation antenna (and associated ADC) of broadband RFI-affected frames. The value returned is the highest of these counters.

A count of ADC frames containing broadband RFI for all dual polarisation antennas can be read using read_broadband_rfi.

Returns:

Maximum number of ADC frames containing broadband RFI

Return type:

int

power_off_preadus()

Power off all preADUs. The two preADUs cannot be powered off independently. Note, this is possible even if one or more preADU is not fitted.

power_on_preadus()

Power on all preADUs. The two preADUs cannot be powered on independently. Note, this is possible even if one or more preADU is not fitted.

property preadu_power_enabled

Check if tile is supplying power to preADUs. Only checks one preADU as their power supply is not independent. Note, this is possible even if a preADU is not fitted.

Returns:

True if a preADUs are being supplied power, else False

Return type:

bool

print_fpga_firmware_information(fpga_id=0)

Print FPGA firmware information.

Parameters:

fpga_id (int) – FPGA ID, 0 or 1

program_fpgas(bitfile)

Program both FPGAs with specified firmware.

Parameters:

bitfile (str) – Bitfile to load

Raises:

LibraryError – bitfile is None type

read_adc_overrange(adcs=range(0, 16), clear=False)

Read the overrange register of the specified ADCs. Optionally clear the register Return a list of length len(adcs); the elements of which are lists of two booleans which correspond to the overrange status of the two ADC channels in the form of [Channel A, Channel B]

Parameters:

• adcs (list(int)) – List of ADCs IDs from which the overrange statuses will be read

• clear (bool) – Clears the register bits after reading if set to true

Returns:

Bidimensional array of overrange status of form [adc_id][adc_channel]

Return type:

list(list(bool))

read_all_live_calibration_coefficients()

Reads live calibration coefficients which is the set of coefficients that were written in load_calibration_coefficients but not in use by the firmware. Coeffiicients are returned for all beams (beamformer channels). calibration_coefs is a tridimensional complex array of the form calibration_coefs[channel, antenna, polarization], with each element representing a normalized coefficient, with (1.0, 0.0) the normal, expected response for an ideal antenna. Channel is the index specifying the channels at the beamformer output, i.e. considering only those channels actually processed and beam assignments. The polarization index ranges from 0 to 3.

• 0: X polarization direct element

• 1: X->Y polarization cross element

• 2: Y->X polarization cross element

• 3: Y polarization direct element

The calibration coefficients may include any rotation matrix (e.g. the parallactic angle), but do not include the geometric delay.

Returns:

Calibration coefficients. array [384, 16, 4]

Return type:

numpy.array(complex)

read_all_staged_calibration_coefficients()

Reads staged calibration coefficients which is the set of coefficients that is currently in use by the firmware. Coeffiicients are returned for all beams (beamformer channels). calibration_coefs is a tridimensional complex array of the form calibration_coefs[channel, antenna, polarization], with each element representing a normalized coefficient, with (1.0, 0.0) the normal, expected response for an ideal antenna. Channel is the index specifying the channels at the beamformer output, i.e. considering only those channels actually processed and beam assignments. The polarization index ranges from 0 to 3.

• 0: X polarization direct element

• 1: X->Y polarization cross element

• 2: Y->X polarization cross element

• 3: Y polarization direct element

The calibration coefficients may include any rotation matrix (e.g. the parallactic angle), but do not include the geometric delay.

Returns:

Calibration coefficients. array [384, 16, 4]

Return type:

numpy.array(complex)

read_antenna_buffer(*args, **kwargs)

read_broadband_rfi(antennas=range(0, 16))

Reads out the broadband RFI counters

Parameters:

antennas (list(int)) – list antennas of which RFI counters to read

Returns:

RFI counters

Return type:

numpy_array[antenna][polarisation]

read_live_calibration_coefficients(antenna)

Reads live calibration coefficients which is the set of coefficients that is currently in use by the firmware. calibration_coefs is a bidimensional complex array of the form calibration_coefs[channel, polarization], with each element representing a normalized coefficient, with (1.0, 0.0) the normal, expected response for an ideal antenna. Channel is the index specifying the channels at the beamformer output, i.e. considering only those channels actually processed and beam assignments. The polarization index ranges from 0 to 3.

• 0: X polarization direct element

• 1: X->Y polarization cross element

• 2: Y->X polarization cross element

• 3: Y polarization direct element

The calibration coefficients may include any rotation matrix (e.g. the parallactic angle), but do not include the geometric delay.

Parameters:

antenna – Antenna number. Integer in range 0:15

Returns:

Calibration coefficients. array [384, 4]

Return type:

list(list(complex))

read_polyfilter_name()

Returns the polyfilter name used in the firmware Note, only checks first FPGA as they should match.

Returns:

string filter name

Return type:

str

read_staged_calibration_coefficients(antenna)

Reads staged calibration coefficients which is the set of coefficients that were written in load_calibration_coefficients but not in use by the firmware calibration_coefs is a bidimensional complex array of the form calibration_coefs[channel, polarization], with each element representing a normalized coefficient, with (1.0, 0.0) the normal, expected response for an ideal antenna. Channel is the index specifying the channels at the beamformer output, i.e. considering only those channels actually processed and beam assignments. The polarization index ranges from 0 to 3.

• 0: X polarization direct element

• 1: X->Y polarization cross element

• 2: Y->X polarization cross element

• 3: Y polarization direct element

The calibration coefficients may include any rotation matrix (e.g. the parallactic angle), but do not include the geometric delay.

Parameters:

antenna – Antenna number. Integer in range 0:15

Returns:

Calibration coefficients. array [384, 4]

Return type:

list(list(complex))

report_sdn_routing(arp_table_entries=None)

Provide a human-readable summary of the 40G network configuration based on the 40G ARP table configuraiton.

Example:

CSP data - even channels (master FPGA)
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:4661 -> 10.132.61.8:4660 via gateway 10.130.7.254

CSP data - odd channels (slave FPGA)
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:4661 -> 10.132.61.8:4662 via gateway 10.130.7.254

LMC raw ADC data
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:61648 -> 10.132.61.8:7660 via gateway 10.130.7.254

LMC synchronised raw ADC data
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:61648 -> 10.132.61.8:7660 via gateway 10.130.7.254

LMC burst channelised data
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:61648 -> 10.132.61.8:7660 via gateway 10.130.7.254

LMC continuous channelised data
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:61648 -> 10.132.61.8:7660 via gateway 10.130.7.254

LMC tile beam data
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:61648 -> 10.132.61.8:7660 via gateway 10.130.7.254

LMC integrated channelised data
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:61648 -> 10.132.61.8:8660 via gateway 10.130.7.254

LMC integrated tile beam data
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:61648 -> 10.132.61.8:8660 via gateway 10.130.7.254

Antenna buffer data
Tile 0 QSFP P1 (Lower):  10.130.5.10/21:61648 -> 10.132.61.8:7660 via gateway 10.130.7.254

Parameters:

arp_table_entries (int | None) – Number of ARP table entries to consider

Returns:

summary of IP and port routing

Return type:

str

reset_eth_errors()

Reset error flags in TPM 40G UDP core.

property rfi_blanking_enabled_antennas

Gets the list of antennas for broadband RFI blanking is currently enabled.

Returns:

list of antennas with RFI blanking enabled

Return type:

list(int)

select_method_to_check_valid_synchronised_data_request(daq_mode, t_request, fpga_id=None)

Checks if Firmware contains the invalid flag register that raises a flag during synchronisation error. If the Firmware has the register then it will read it to check that the timestamp request was valid. If the register is not present, the software method will be used to calculate if the timestamp request was valid

Parameters:

• daq_mode (str) – string used to select which Flag register of the LMC to read

• t_request (int) – requested timestamp. Must be more than current timestamp to be synchronised successfuly

• fpga_id (int) – FPGA_ID, 0 or 1. Default None

send_beam_data(timeout=0, timestamp=None, seconds=0.2)

Send beam data from the TPM.

Parameters:

• timeout (int) – When to stop

• timestamp (int) – When to send

• seconds (float) – When to synchronise

send_channelised_data(number_of_samples=1024, first_channel=0, last_channel=511, timestamp=None, seconds=0.4)

Send channelised data from the TPM.

Parameters:

• number_of_samples (int) – Number of spectra to send

• first_channel (int) – First channel to send

• last_channel (int) – Last channel to send

• timestamp (int) – When to start transmission

• seconds (float) – When to synchronise

send_channelised_data_continuous(channel_id, number_of_samples=128, wait_seconds=0, timestamp=None, seconds=0.2)

Continuously send channelised data from a single channel.

Parameters:

• channel_id (int) – Channel ID

• number_of_samples (int) – Number of spectra to send

• wait_seconds (int) – Wait time before sending data

• timestamp (int) – When to start

• seconds (float) – When to synchronise

send_channelised_data_narrowband(frequency, round_bits, number_of_samples=128, wait_seconds=0, timestamp=None, seconds=0.2)

Continuously send channelised data from a single channel.

Parameters:

• frequency (float) – Sky frequency to transmit

• round_bits (int) – Specify which bits to round

• number_of_samples (int) – Number of spectra to send

• wait_seconds (int) – Wait time before sending data

• timestamp (int) – When to start

• seconds (float) – When to synchronise

send_raw_data(sync=False, timestamp=None, seconds=0.2, fpga_id=None)

Send raw data from the TPM.

Parameters:

• sync (bool) – Synchronised flag

• timestamp (int) – When to start

• seconds (float) – Delay

• fpga_id (int) – Specify which FPGA should transmit, 0,1, or None for both FPGAs

send_raw_data_synchronised(timestamp=None, seconds=0.2)

Send synchronised raw data.

Parameters:

• timestamp (int) – When to start

• seconds (float) – Period

set_adc_test_pattern(pattern=[[15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128], [15, 67, 252, 128]], adcs=range(0, 16))

Configure ADC Test Pattern User Input.

This is used when the ADC Test Mode is configured as fixed. See the enable_test_mode method above.

Parameters:

• pattern (list(list(int))) – List of four integer values to be applied per ADC

• adcs (list(int)) – List of ADC IDs to be configured

set_beamformer_epoch(epoch)

Set the Unix epoch in seconds since Unix reference time.

Parameters:

epoch (int) – Unix epoch for the reference time

Returns:

Success status

Return type:

bool

set_beamformer_regions(region_array)

Set frequency regions. Define the beamformer regions in the channelizer, with all the parameters for each region. Regions are defined in a 2-d array, for a maximum of 16 (48) regions. Each element in the array defines a region, with the form [start_ch, nof_ch, beam_index]

• start_ch: region starting channel (currently must be a multiple of 2, LS bit discarded).

• nof_ch: size of the region: must be multiple of 8 chans.

• beam_index: beam used for this region, range [0:8).

• subarray_id: ID of the subarray [1:48].

• subarray_logical_channel: Logical channel in the subarray it is the same for all (sub)stations in the subarray. Defaults to station logical channel.

• subarray_beam_id: ID of the subarray beam. Defaults to beam index.

• substation_ID: ID of the substation. Defaults to 0 (no substation).

• aperture_id: ID of the aperture (station*100+substation?). Defaults to antenna ID = 1, substation ID.

Total number of channels must be <= 384.

Parameters:

region_array (list(list(int))) – list of region array descriptors

set_broadband_rfi_factor(rfi_factor=1.0)

Sets the RFI factor for broadband RFI detection, the higher the RFI factor the less RFI is detected/flagged.

This is because data is flagged if the short term power is greater than the long term power * RFI factor * 32/27

Parameters:

rfi_factor (float) – the sensitivity value for the RFI detection

set_c2c_burst()

Setting C2C burst when supported by FPGAs and CPLD.

set_channeliser_truncation(trunc)

Set channeliser truncation scale for the whole tile or for individual ADC channels.

Parameters:

trunc (int or list(int)) – Truncted bits, channeliser output scaled down by specified number of bits. May be a single value (same for all frequency channels) or list of 512 values.

set_csp_download(src_port=None, dst_ip_1=None, dst_ip_2=None, dst_port=None, is_last=False, netmask=None, gateway=None)

Set CSP Destination. This determines where the station beams will be sent to on the Science Data Network.

Note that the netmask and gateway configurations are common to the entire FortyG core. TODO: Should these be removed and set once in set_xg_eth_configuration?

Parameters:

• src_port (int) – Source port

• dst_ip_1 (int | str) – Destination IP FPGA1

• dst_ip_2 (int | str) – Destination IP FPGA2

• dst_port (int) – Destination port

• is_last (bool) – True for last tile in beamforming chain

• netmask (int | str) – Netmask

• gateway (int | str) – Gateway IP

set_csp_rounding(rounding)

Set output rounding for CSP.

Parameters:

rounding (int) – Number of bits rounded in final 8 bit requantization to CSP

Returns:

success status

Return type:

bool

set_first_last_tile(is_first, is_last)

Defines if a tile is first, last, both or intermediate.

One, and only one tile must be first, and last, in a chain. A tile can be both (one tile chain), or none.

Parameters:

• is_first (bool) – True for first tile in beamforming chain

• is_last (bool) – True for last tile in beamforming chain

Returns:

success status

Return type:

bool

set_fpga_time(device, device_time)

Set Unix time in FPGA.

Parameters:

• device (Device) – FPGA to get time from

• device_time (int) – Internal time for FPGA

Raises:

LibraryError – Invalid value for device

set_intTime(integrationTime=0.01)

Set integration time (and discard bits) for total power. This is the time period over which the ADC power is averaged to get the RMS.

Parameters:

integrationTime (float) – the integration time period in seconds

set_lmc_download(mode, data_type=None, payload_length=None, dst_ip='10.0.10.1', src_port=61648, dst_port=4660, netmask_40g=None, gateway_ip_40g=None)

Configure link and size of control data for LMC packets.

For payload_length, if no value is provided then the value remains unchanged. If no previous value has been provided the firmware default of 1024 will be used.

By default the destination is applied for all LMC packets. Use the data_type argument to configure separately. This functionality is only available when mode is “10g”.

Note that the mode configuration is shared for all data types.

Note that the netmask and gateway configurations are common to the entire FortyG core. TODO: Should these be removed and set once in set_xg_eth_configuration?

Parameters:

• mode (str) – “1g” or “10g” (1G means NSDN, 10G means 40G SDN, needs refactored)

• data_type (str | None) – Specify which data type to configure, or None for all.

• payload_length (int) – SPEAD payload length in bytes

• dst_ip (int | str) – Destination IP

• src_port (int) – Source port

• dst_port (int) – Destination port

• netmask_40g (int | str) – Netmask (40G only)

• gateway_ip_40g (int | str) – Gateway IP (40G only)

set_lmc_integrated_download(mode, data_type=None, channel_payload_length=None, beam_payload_length=None, dst_ip='10.0.10.1', src_port=61648, dst_port=4660, netmask_40g=None, gateway_ip_40g=None)

Configure link and size of control data for integrated LMC packets.

For channel_payload_length and beam_payload_length, if no value is provided then the value remains unchanged. If no previous value has been provided the firmware default of 1024 will be used.

By default both channel and beam integrated packets are configured. Use the data_type argument to configure separately. This functionality is only available when mode is “10g”.

Note that the mode configuration is shared for all data types.

Note that the netmask and gateway configurations are common to the entire FortyG core. TODO: Should these be removed and set once in set_xg_eth_configuration?

Parameters:

• mode (str) – “1g” or “10g” (1G means NSDN, 10G means 40G SDN, needs refactored)

• data_type (str | None) – Specify which data type to configure, “channel”, “beam”, or None for both.

• channel_payload_length (int | None) – SPEAD payload length for integrated channel data

• beam_payload_length (int | None) – SPEAD payload length for integrated beam data

• dst_ip (int | str) – Destination IP

• src_port (int) – Source port

• dst_port (int) – Destination port

• netmask_40g (int | str) – Netmask (40G only)

• gateway_ip_40g (int | str) – Gateway IP (40G only)

set_multi_channel_dst_ip(dst_ip, destination_id)

Set destination IP for a multichannel destination ID.

Parameters:

• dst_ip (int) – Destination IP address

• destination_id (int) – 40G destination ID

set_multi_channel_tx(instance_id, channel_id, destination_id)

Set multichannel transmitter instance.

Parameters:

• instance_id (int) – Transmitter instance ID

• channel_id (int) – Channel ID

• destination_id (int) – 40G destination ID

set_pattern(stage, pattern, adders, start=False, shift=0, zero=0)

Configure the TPM pattern generator.

A signal is injected at a given stage during the signal chain, in a time series dictated by the pattern. This pattern is then applied to all antennas and polarisations via the adders. Thus the overall signal is the sum of the pattern and adders for each antenna/polarisation.

Parameters:

• stage (str) – The stage in the signal chain where the pattern is injected. Options are: ‘jesd’ (output of ADCs), ‘channel’ (output of channelizer), or ‘beamf’ (output of tile beamformer).

• pattern (list[int]) – The data pattern in time order. This must be a list of integers with a length between 1 and 1024. The pattern represents values in time order (not antennas or polarizations).

• adders (list[int]) – A list of 32 integers that expands the pattern to cover 16 antennas and 2 polarizations in hardware. This list maps the pattern to the corresponding signals for the antennas and polarizations.

• start (bool) – Boolean flag indicating whether to start the pattern immediately. If False, the pattern will need to be started manually later.

• shift (int) – Optional bit shift (divides the pattern by 2^shift). This must not be used in the ‘beamf’ stage, where it is always overridden to 4. The default value is 0.

• zero (int) – An integer (0-65535) used as a mask to disable the pattern on specific antennas and polarizations. The same mask is applied to both FPGAs, supporting up to 8 antennas and 2 polarizations. The default value is 0.

set_phase_terminal_count(value)

Set PPS phase terminal count.

Parameters:

value (int) – PPS phase terminal count

set_pointing_delay(delay_array, beam_index)

Specifies the delay in seconds and the delay rate in seconds/seconds. The delay_array specifies the delay and delay rate for each antenna. beam_index specifies which beam is described from (current range 0-47) Delay is updated inside the delay engine at the time specified by method load_delay.

Parameters:

• delay_array (list(list(float))) – delay and delay rate for each antenna

• beam_index (int) – specifies which beam is described (range 0-47)

set_pps_sampling(target, margin)

Set the PPS sampler terminal count.

Parameters:

• target (int) – target delay

• margin (int) – margin, target +- margin

set_preadu_attenuation(attenuation)

Set same preadu attenuation in all preadus.

Parameters:

attenuation (int) – Desired attenuation

set_preadu_levels(levels)

Set preADU attenuation levels.

Parameters:

levels (list of float) – Desired attenuation levels for each ADC channel, in dB.

set_spead_format(ska_spead_header_format)

Set CSP SPEAD format.

Parameters:

ska_spead_header_format (bool) – True for new (SKA) format, False for old (AAVS) format

Raises:

LibraryError – Invalid value for device

set_station_id(station_id, tile_id)

Set station ID.

Parameters:

• station_id (int) – Station ID

• tile_id (int) – Tile ID within station

set_test_generator_pulse(freq_code, amplitude=0.0)

Test generator Gaussian white noise setting.

Parameters:

• freq_code (int) – Code for pulse frequency. Range 0 to 7: 16,12,8,6,4,3,2 times frame frequency

• amplitude (float) – Tone peak amplitude, normalized to 127.5 ADC units, resolution 0.5 ADU

set_time_delays(delays)

Set coarse zenith delay for input ADC streams. Delay specified in nanoseconds, nominal is 0.

Parameters:

delays (list(float)) – Delay in samples, positive delay adds delay to the signal stream

Returns:

Parameters in range

Return type:

bool

set_up_antenna_buffer(*args, **kwargs)

set_xg_eth_configuration(src_ip_fpga1=None, src_ip_fpga2=None, qsfp_detection='auto', active_40g_ports_setting='port1-only')

Set source IP/MAC/ports for 40G cores. Configure active 40G QSFP interfaces & cores based on auto detection and active port settings.

Parameters:

• src_ip_fpga1 (str) – source IP address for FPGA1 40G interface

• src_ip_fpga2 (str) – source IP address for FPGA2 40G interface

• qsfp_detection (str) – QSFP auto detection setting

• active_40g_ports_setting (str) – Active QSFP interface setting

Raises:

BoardError – if a required QSFP module is not plugged.

property ska_spead_header

property spead_ska_format_supported: bool

Check if new (SKA) format for CSP SPEAD header is supported.

Returns:

True if new (SKA) format for CSP SPEAD header is supported

Return type:

bool

start_40g_test(single_packet_mode=False, ipg=32)

Starts the 40G loopback test between the two TPM FPGAs. Both TPM QSFP must be active and able to transmit and receive to each other to start the test. For multi-tile variants of this test, see SPS Test Suite.

Parameters:

• single_packet_mode (bool) – Only transmit a single packet

• ipg (int) – Inter packet gap

Returns:

Test start pass (0) or fail (1)

Return type:

int

start_acquisition(start_time=None, delay=2, global_start_time=None)

Start data acquisition.

Start the TPM signal processing pipeline at start time (default = now)+delay If global_start_time is specified, the TPM internal timing simulates a start_acquisition at the specified time. This defaults to the latest multiple of 864 seconds since the TAI 2000 epoch, including leap seconds, before start time.

Parameters:

• start_time (int) – Time for starting (seconds)

• delay (int) – delay after start_time (seconds)

• global_start_time (int) – TPM will act as if it is started at this time (seconds)

Raises:

LibraryError – Acquisition already started

start_antenna_buffer(*args, **kwargs)

start_beamformer(start_time=0, duration=-1, scan_id=0, mask=None, beam=None, channel_groups=None)

Start the beamformer. Duration: if > 0 is a duration in frames * 256 (276.48 us) if == -1 run forever

Parameters:

• start_time (int) – time (in ADC frames/256) for first frame sent

• duration (int) – duration in ADC frames/256. Multiple of 8

• scan_id (int) – ID of the scan, to be specified in the CSP SPEAD header

• mask (int) – Bitmask of the channels to be started. Ignored if beam is specified

• beam (int | None) – Beam number to start. Computes mask using beam table

Returns:

False for error (e.g. beamformer already running)

Rtype bool:

start_multi_channel_tx(instances, timestamp=None, seconds=0.2)

Start multichannel data transmission from the TPM.

Parameters:

• instances (int) – 64 bit integer, each bit addresses the corresponding TX transmitter

• timestamp (int) – Start time

• seconds (float) – synchronisation delay ID

start_pattern(stage)

Start the data pattern for the specified stage or for all stages.

Parameters:

stage (str) – The stage in the signal chain where the pattern is to be started. Options are ‘jesd’, ‘channel’, or ‘beamf’. If ‘all’ is provided, it starts the pattern on all stages.

stop_40g_test()

Stop 40G embedded test.

stop_antenna_buffer(*args, **kwargs)

stop_beamformer(mask=None, beam=None, channel_groups=None)

Stop the beamformer for a given beam or set of channels, default for all. Specification may be any of the following, in order of priority:

Parameters:

• beam (int | None) – Beam number to start. Computes the mask using beam table

• channel_groups (list | None) – list of channel groups, in range 0:48. group 0 for channels 0-7, to group 47 for channels 380-383

• mask (int) – Bitmask of the channels to be started. Ignored if beam is specified

stop_channelised_data_continuous()

Stop sending channelised data.

stop_data_transmission()

Stop all LMC (non integrated) data transmission from TPM.

stop_integrated_beam_data()

Stop transmission of integrated beam data.

stop_integrated_channel_data()

Stop transmission of integrated channel data.

stop_integrated_data()

Stop transmission of integrated data.

stop_multi_channel_tx()

Stop multichannel TX data transmission

stop_pattern(stage)

Stop the data pattern for the specified stage or for all stages.

Parameters:

stage (str) – The stage in the signal chain where the pattern is to be stopped. Options are ‘jesd’, ‘channel’, or ‘beamf’. If ‘all’ is provided, it stops the pattern on all stages.

switch_calibration_bank(switch_time=0)

Switches the loaded calibration coefficients at prescribed time If time = 0 switch immediately.

Parameters:

switch_time (int) – time (in ADC frames/256) for delay update

sync_fpga_time(use_internal_pps=False, pps_period=1)

Set UTC time to two FPGAs in the tile Returns when these are synchronised.

Parameters:

use_internal_pps (bool) – use internally generated PPS, for test/debug

synchronised_data_operation(seconds=0.2, timestamp=None)

Synchronise data operations between FPGAs.

Parameters:

• seconds (float) – Number of seconds to delay operation

• timestamp (int) – Timestamp at which tile will be synchronised

Returns:

timestamp written into FPGA timestamp request register

Return type:

int

test_generator_disable_tone(generator)

Test generator: disable tone. Set tone amplitude and frequency to 0.

Parameters:

generator (int) – generator select. 0 or 1

test_generator_input_select(inputs)

Specify ADC inputs which are substitute to test signal. Specified using a 32 bit mask, with LSB for ADC input 0.

Parameters:

inputs (int) – Bit mask of inputs using test signal

test_generator_set_delay(delays)

Set the delays in the test generator.

Parameters:

delays (float) – a 32 long list of floats.

test_generator_set_noise(amplitude=0.0, load_time=0)

Test generator Gaussian white noise setting.

Parameters:

• amplitude (float) – Tone peak amplitude, normalized to 26.03 ADC units, resolution 0.102 ADU

• load_time (int) – Time to start the tone.

test_generator_set_tone(generator, frequency=100000000.0, amplitude=0.0, phase=0.0, load_time=0)

Test generator tone setting.

Parameters:

• generator (int) – generator select. 0 or 1

• frequency (float) – Tone frequency in Hz

• amplitude (float) – Tone peak amplitude, normalized to 31.875 ADC units, resolution 0.125 ADU

• phase (float) – Initial tone phase, in turns

• load_time (int) – Time to start the tone.

tpm_communication_check()

Brute force check to make sure we can communicate with programmed TPM.

tpm_version()

Determine whether this is a TPM V1.2 or TPM V1.6.

Returns:

TPM hardware version

Return type:

str

wait_pps_event()

Wait for a PPS edge. Added timeout feture to avoid method to stuck.

Raises:

BoardError – Hardware PPS stuck

ska_low_sps_tpm_api.tile.connected(f)

Helper to disallow certain function calls on unconnected tiles.

Parameters:

f (callable) – the method wrapped by this helper

Returns:

the wrapped method

Return type:

callable

Hardware functions for monitoring of TPM hardware health status.

class ska_low_sps_tpm_api.tile_health_monitor.TileHealthMonitor

Tile Health Monitor Mixin Class, must be inherited by Tile Class

all_monitoring_categories()

Returns a list of all monitoring point ‘categories’. Here categories is a super-set of monitoring points and is the full list of accepted strings to define_monitoring_point_filter(). For example, the monitoring point: io.udp_interface.crc_error_count.FPGA0 would have the associated categories: 'io', 'io.udp_interface', 'io.udp_interface.crc_error_count', 'io.udp_interface.crc_error_count.FPGA0'.

Example:

>>> tile.all_monitoring_categories()

[
  "adcs",
  "adcs.pll_status",
  "adcs.pll_status.ADC0",
  "adcs.pll_status.ADC1",
  "adcs.pll_status.ADC10",
  "adcs.pll_status.ADC11",
  "adcs.pll_status.ADC12",
  "adcs.pll_status.ADC13",
  "adcs.pll_status.ADC14",
  "adcs.pll_status.ADC15",
  "adcs.pll_status.ADC2",
  "adcs.pll_status.ADC3",
  "adcs.pll_status.ADC4",
  "adcs.pll_status.ADC5",
  "adcs.pll_status.ADC6",
  "adcs.pll_status.ADC7",
  "adcs.pll_status.ADC8",
  "adcs.pll_status.ADC9",
  "adcs.sysref_counter",
  "adcs.sysref_counter.ADC0",
  "adcs.sysref_counter.ADC1",
  "adcs.sysref_counter.ADC10",
  "adcs.sysref_counter.ADC11",
  "adcs.sysref_counter.ADC12",
  "adcs.sysref_counter.ADC13",
  "adcs.sysref_counter.ADC14",
  "adcs.sysref_counter.ADC15",
  "adcs.sysref_counter.ADC2",
  "adcs.sysref_counter.ADC3",
  "adcs.sysref_counter.ADC4",
  "adcs.sysref_counter.ADC5",
  "adcs.sysref_counter.ADC6",
  "adcs.sysref_counter.ADC7",
  "adcs.sysref_counter.ADC8",
  "adcs.sysref_counter.ADC9",
  "adcs.sysref_timing_requirements",
  "adcs.sysref_timing_requirements.ADC0",
  "adcs.sysref_timing_requirements.ADC1",
  "adcs.sysref_timing_requirements.ADC10",
  "adcs.sysref_timing_requirements.ADC11",
  "adcs.sysref_timing_requirements.ADC12",
  "adcs.sysref_timing_requirements.ADC13",
  "adcs.sysref_timing_requirements.ADC14",
  "adcs.sysref_timing_requirements.ADC15",
  "adcs.sysref_timing_requirements.ADC2",
  "adcs.sysref_timing_requirements.ADC3",
  "adcs.sysref_timing_requirements.ADC4",
  "adcs.sysref_timing_requirements.ADC5",
  "adcs.sysref_timing_requirements.ADC6",
  "adcs.sysref_timing_requirements.ADC7",
  "adcs.sysref_timing_requirements.ADC8",
  "adcs.sysref_timing_requirements.ADC9",
  "alarms",
  "currents",
  "currents.FE0_mVA",
  "currents.FE1_mVA",
  "dsp",
  "dsp.max_broadband_rfi",
  "dsp.station_beamf",
  "dsp.station_beamf.ddr_parity_error_count",
  "dsp.station_beamf.discarded_or_flagged_packet_count",
  "dsp.station_beamf.dsp_latency_error",
  "dsp.station_beamf.status",
  "dsp.tile_beamf",
  "io",
  "io.data_router",
  "io.data_router.discarded_packets",
  "io.data_router.status",
  "io.ddr_interface",
  "io.ddr_interface.initialisation",
  "io.ddr_interface.rd_cnt",
  "io.ddr_interface.rd_cnt.FPGA0",
  "io.ddr_interface.rd_cnt.FPGA1",
  "io.ddr_interface.rd_dat_cnt",
  "io.ddr_interface.rd_dat_cnt.FPGA0",
  "io.ddr_interface.rd_dat_cnt.FPGA1",
  "io.ddr_interface.reset_counter",
  "io.ddr_interface.reset_counter.FPGA0",
  "io.ddr_interface.reset_counter.FPGA1",
  "io.ddr_interface.wr_cnt",
  "io.ddr_interface.wr_cnt.FPGA0",
  "io.ddr_interface.wr_cnt.FPGA1",
  "io.f2f_interface",
  "io.f2f_interface.hard_error",
  "io.f2f_interface.pll_status",
  "io.f2f_interface.soft_error",
  "io.jesd_interface",
  "io.jesd_interface.lane_error_count",
  "io.jesd_interface.lane_error_count.FPGA0",
  "io.jesd_interface.lane_error_count.FPGA0.Core0",
  "io.jesd_interface.lane_error_count.FPGA0.Core1",
  "io.jesd_interface.lane_error_count.FPGA1",
  "io.jesd_interface.lane_error_count.FPGA1.Core0",
  "io.jesd_interface.lane_error_count.FPGA1.Core1",
  "io.jesd_interface.lane_status",
  "io.jesd_interface.link_status",
  "io.jesd_interface.qpll_status",
  "io.jesd_interface.qpll_status.FPGA0",
  "io.jesd_interface.qpll_status.FPGA1",
  "io.jesd_interface.resync_count",
  "io.jesd_interface.resync_count.FPGA0",
  "io.jesd_interface.resync_count.FPGA1",
  "io.udp_interface",
  "io.udp_interface.arp",
  "io.udp_interface.bip_error_count",
  "io.udp_interface.bip_error_count.FPGA0",
  "io.udp_interface.bip_error_count.FPGA1",
  "io.udp_interface.crc_error_count",
  "io.udp_interface.crc_error_count.FPGA0",
  "io.udp_interface.crc_error_count.FPGA1",
  "io.udp_interface.decode_error_count",
  "io.udp_interface.decode_error_count.FPGA0",
  "io.udp_interface.decode_error_count.FPGA1",
  "io.udp_interface.linkup_loss_count",
  "io.udp_interface.linkup_loss_count.FPGA0",
  "io.udp_interface.linkup_loss_count.FPGA1",
  "io.udp_interface.status",
  "temperatures",
  "temperatures.ADC0",
  "temperatures.ADC1",
  "temperatures.ADC10",
  "temperatures.ADC11",
  "temperatures.ADC12",
  "temperatures.ADC13",
  "temperatures.ADC14",
  "temperatures.ADC15",
  "temperatures.ADC2",
  "temperatures.ADC3",
  "temperatures.ADC4",
  "temperatures.ADC5",
  "temperatures.ADC6",
  "temperatures.ADC7",
  "temperatures.ADC8",
  "temperatures.ADC9",
  "temperatures.FPGA0",
  "temperatures.FPGA1",
  "temperatures.board",
  "timing",
  "timing.clock_managers",
  "timing.clock_managers.FPGA0",
  "timing.clock_managers.FPGA0.C2C_MMCM",
  "timing.clock_managers.FPGA0.DSP_MMCM",
  "timing.clock_managers.FPGA0.JESD_MMCM",
  "timing.clock_managers.FPGA1",
  "timing.clock_managers.FPGA1.C2C_MMCM",
  "timing.clock_managers.FPGA1.DSP_MMCM",
  "timing.clock_managers.FPGA1.JESD_MMCM",
  "timing.clocks",
  "timing.clocks.FPGA0",
  "timing.clocks.FPGA0.DDR",
  "timing.clocks.FPGA0.JESD",
  "timing.clocks.FPGA0.UDP",
  "timing.clocks.FPGA1",
  "timing.clocks.FPGA1.DDR",
  "timing.clocks.FPGA1.JESD",
  "timing.clocks.FPGA1.UDP",
  "timing.pll",
  "timing.pll_40g",
  "timing.pps",
  "timing.pps.status",
  "timing.timestamp",
  "timing.timestamp.FPGA0",
  "timing.timestamp.FPGA1",
  "voltages",
  "voltages.AVDD3",
  "voltages.DDR0_VREF",
  "voltages.DDR1_VREF",
  "voltages.MAN_1V2",
  "voltages.MGT_AVCC",
  "voltages.MGT_AVTT",
  "voltages.MON_1V8",
  "voltages.MON_3V3",
  "voltages.MON_5V0",
  "voltages.SW_AVDD1",
  "voltages.SW_AVDD2",
  "voltages.VIN",
  "voltages.VM_AGP0",
  "voltages.VM_AGP1",
  "voltages.VM_AGP2",
  "voltages.VM_AGP3",
  "voltages.VM_AGP4",
  "voltages.VM_AGP5",
  "voltages.VM_AGP6",
  "voltages.VM_AGP7",
  "voltages.VM_CLK0B",
  "voltages.VM_CLK1B",
  "voltages.VM_DDR0_VTT",
  "voltages.VM_DDR1_VDD",
  "voltages.VM_DDR1_VTT",
  "voltages.VM_DRVDD",
  "voltages.VM_DVDD",
  "voltages.VM_FE0",
  "voltages.VM_FE1",
  "voltages.VM_MGT0_AUX",
  "voltages.VM_MGT1_AUX",
  "voltages.VM_PLL",
  "voltages.VM_SW_AMP"
]

Returns:

list of categories

Return type:

list of str

all_monitoring_points()

Returns a list of all monitoring points by finding all leaf nodes in the lookup dict that have a corresponding method field.

The monitoring points returned are strings produced from . delimited keys. For example: 'voltages.5V0', 'io.udp_interface.crc_error_count.FPGA0'

Example:

>>> tile.all_monitoring_points()

[
  "temperatures.board",
  "temperatures.FPGA0",
  "temperatures.FPGA1",
  "temperatures.ADC0",
  "temperatures.ADC1",
  "temperatures.ADC2",
  "temperatures.ADC3",
  "temperatures.ADC4",
  "temperatures.ADC5",
  "temperatures.ADC6",
  "temperatures.ADC7",
  "temperatures.ADC8",
  "temperatures.ADC9",
  "temperatures.ADC10",
  "temperatures.ADC11",
  "temperatures.ADC12",
  "temperatures.ADC13",
  "temperatures.ADC14",
  "temperatures.ADC15",
  "voltages.MGT_AVCC",
  "voltages.MGT_AVTT",
  "voltages.SW_AVDD1",
  "voltages.SW_AVDD2",
  "voltages.AVDD3",
  "voltages.MAN_1V2",
  "voltages.DDR0_VREF",
  "voltages.DDR1_VREF",
  "voltages.VM_DRVDD",
  "voltages.VIN",
  "voltages.MON_3V3",
  "voltages.MON_1V8",
  "voltages.MON_5V0",
  "voltages.VM_AGP0",
  "voltages.VM_AGP1",
  "voltages.VM_AGP2",
  "voltages.VM_AGP3",
  "voltages.VM_CLK0B",
  "voltages.VM_DDR0_VTT",
  "voltages.VM_FE0",
  "voltages.VM_MGT0_AUX",
  "voltages.VM_PLL",
  "voltages.VM_AGP4",
  "voltages.VM_AGP5",
  "voltages.VM_AGP6",
  "voltages.VM_AGP7",
  "voltages.VM_CLK1B",
  "voltages.VM_DDR1_VDD",
  "voltages.VM_DDR1_VTT",
  "voltages.VM_DVDD",
  "voltages.VM_FE1",
  "voltages.VM_MGT1_AUX",
  "voltages.VM_SW_AMP",
  "currents.FE0_mVA",
  "currents.FE1_mVA",
  "alarms",
  "adcs.pll_status.ADC0",
  "adcs.pll_status.ADC1",
  "adcs.pll_status.ADC2",
  "adcs.pll_status.ADC3",
  "adcs.pll_status.ADC4",
  "adcs.pll_status.ADC5",
  "adcs.pll_status.ADC6",
  "adcs.pll_status.ADC7",
  "adcs.pll_status.ADC8",
  "adcs.pll_status.ADC9",
  "adcs.pll_status.ADC10",
  "adcs.pll_status.ADC11",
  "adcs.pll_status.ADC12",
  "adcs.pll_status.ADC13",
  "adcs.pll_status.ADC14",
  "adcs.pll_status.ADC15",
  "adcs.sysref_timing_requirements.ADC0",
  "adcs.sysref_timing_requirements.ADC1",
  "adcs.sysref_timing_requirements.ADC2",
  "adcs.sysref_timing_requirements.ADC3",
  "adcs.sysref_timing_requirements.ADC4",
  "adcs.sysref_timing_requirements.ADC5",
  "adcs.sysref_timing_requirements.ADC6",
  "adcs.sysref_timing_requirements.ADC7",
  "adcs.sysref_timing_requirements.ADC8",
  "adcs.sysref_timing_requirements.ADC9",
  "adcs.sysref_timing_requirements.ADC10",
  "adcs.sysref_timing_requirements.ADC11",
  "adcs.sysref_timing_requirements.ADC12",
  "adcs.sysref_timing_requirements.ADC13",
  "adcs.sysref_timing_requirements.ADC14",
  "adcs.sysref_timing_requirements.ADC15",
  "adcs.sysref_counter.ADC0",
  "adcs.sysref_counter.ADC1",
  "adcs.sysref_counter.ADC2",
  "adcs.sysref_counter.ADC3",
  "adcs.sysref_counter.ADC4",
  "adcs.sysref_counter.ADC5",
  "adcs.sysref_counter.ADC6",
  "adcs.sysref_counter.ADC7",
  "adcs.sysref_counter.ADC8",
  "adcs.sysref_counter.ADC9",
  "adcs.sysref_counter.ADC10",
  "adcs.sysref_counter.ADC11",
  "adcs.sysref_counter.ADC12",
  "adcs.sysref_counter.ADC13",
  "adcs.sysref_counter.ADC14",
  "adcs.sysref_counter.ADC15",
  "timing.clocks.FPGA0.JESD",
  "timing.clocks.FPGA0.DDR",
  "timing.clocks.FPGA0.UDP",
  "timing.clocks.FPGA1.JESD",
  "timing.clocks.FPGA1.DDR",
  "timing.clocks.FPGA1.UDP",
  "timing.clock_managers.FPGA0.C2C_MMCM",
  "timing.clock_managers.FPGA0.JESD_MMCM",
  "timing.clock_managers.FPGA0.DSP_MMCM",
  "timing.clock_managers.FPGA1.C2C_MMCM",
  "timing.clock_managers.FPGA1.JESD_MMCM",
  "timing.clock_managers.FPGA1.DSP_MMCM",
  "timing.timestamp.FPGA0",
  "timing.timestamp.FPGA1",
  "timing.pps.status",
  "timing.pll",
  "timing.pll_40g",
  "io.jesd_interface.link_status",
  "io.jesd_interface.lane_error_count.FPGA0.Core0",
  "io.jesd_interface.lane_error_count.FPGA0.Core1",
  "io.jesd_interface.lane_error_count.FPGA1.Core0",
  "io.jesd_interface.lane_error_count.FPGA1.Core1",
  "io.jesd_interface.lane_status",
  "io.jesd_interface.resync_count.FPGA0",
  "io.jesd_interface.resync_count.FPGA1",
  "io.jesd_interface.qpll_status.FPGA0",
  "io.jesd_interface.qpll_status.FPGA1",
  "io.ddr_interface.initialisation",
  "io.ddr_interface.reset_counter.FPGA0",
  "io.ddr_interface.reset_counter.FPGA1",
  "io.ddr_interface.rd_cnt.FPGA0",
  "io.ddr_interface.rd_cnt.FPGA1",
  "io.ddr_interface.wr_cnt.FPGA0",
  "io.ddr_interface.wr_cnt.FPGA1",
  "io.ddr_interface.rd_dat_cnt.FPGA0",
  "io.ddr_interface.rd_dat_cnt.FPGA1",
  "io.f2f_interface.pll_status",
  "io.f2f_interface.soft_error",
  "io.f2f_interface.hard_error",
  "io.udp_interface.arp",
  "io.udp_interface.status",
  "io.udp_interface.crc_error_count.FPGA0",
  "io.udp_interface.crc_error_count.FPGA1",
  "io.udp_interface.bip_error_count.FPGA0",
  "io.udp_interface.bip_error_count.FPGA1",
  "io.udp_interface.decode_error_count.FPGA0",
  "io.udp_interface.decode_error_count.FPGA1",
  "io.udp_interface.linkup_loss_count.FPGA0",
  "io.udp_interface.linkup_loss_count.FPGA1",
  "io.data_router.status",
  "io.data_router.discarded_packets",
  "dsp.tile_beamf",
  "dsp.station_beamf.status",
  "dsp.station_beamf.discarded_or_flagged_packet_count",
  "dsp.station_beamf.ddr_parity_error_count",
  "dsp.station_beamf.dsp_latency_error",
  "dsp.max_broadband_rfi"
]

Returns:

list of monitoring points

Return type:

list of str

check_ad9528_pll_status()

Status of TPM AD9528 PLL chip. The AD9528 contains two PLLs; the first PLL PLL1 generates a 100 MHz clock which is locked to the External 10 MHz reference clock provided by the subrack. The generated 100 MHz clock is forwarded to the FPGA as the primary reference clock and is also used by the second PLL PLL2 in the AD9528 to generate the 800 MHz ADC sampling clock.

Example: ( current_status, historical_status_counter )

current_status: The current PLL lock status.

• True → Both PLL1 and PLL2 are locked as expected.

• False → Either PLL1, PLL2 or both are not currently locked.

historical_status_counter: To detect transient loss of the PLL lock that occurs for less than 1 second, there is also the historical loss of lock counter. This counts the number of loss of lock events since the last query.

• 0 → No loss of PLL lock events have occured since the last query.

• N > 0 → N loss of PLL lock events have occured since the last query.

NOTE: The loss of lock counter increments for a loss of lock event on either PLL1 or PLL2 of the AD9528.

Returns:

current lock status and lock loss counter value

Return type:

tuple

check_ad9550_pll_status()

Status of TPM AD9550 PLL chip. The AD9550 generates a 156.25 MHz clock used for the FPGA 40GbE UDP clock.

Example: ( current_status, historical_status_counter )

current_status: The current PLL lock status.

• True → PLL is currently locked as expected.

• False → PLL is not currently locked.

historical_status_counter: To detect transient loss of the PLL lock that occurs for less than 1 second, there is also the historical loss of lock counter. This counts the number of loss of lock events since the last query.

• 0 → No loss of PLL lock events have occured since the last query.

• N > 0 → N loss of PLL lock events have occured since the last query.

Returns:

current lock status and lock loss counter value

Return type:

tuple

check_adc_pll_status(adc_id=None)

Status of ADC PLL.

Example: ( current_status, historical_status )

current_status: The current PLL lock status.

• True → PLL is currently locked as expected.

• False → PLL is not currently locked.

historical_status: To detect transient loss of the PLL lock that occurs for less than 1 second, there is also the historical loss of lock flag.

• True → No loss of PLL lock events have occured since the last query.

• False → One or more loss of PLL lock events have occured since the last

  query.

Parameters:

adc_id (int) – Specify which ADC, 0-15, None for all ADCs

Returns:

(True, True) if lock is up and no loss of lock

Return type:

dict of tuple with an entry for each ADC

check_adc_sysref_counter(adc_id=None, show_info=True)

Checks ADC SYSREF counter is incrementing.

SYSREF counter increments for each SYSREF event and overflows at 255, approx. every 3.28ms.

Returns True if counter is incrementing.

Will retry for 1 second until two readings can be taken in under 3ms to guarantee an overflow does not occur while taking the measurement.

Parameters:

• adc_id (int) – Specify which ADC, 0-15, None for all ADCs

• show_info (bool) – log counter reading and elapsed time for each reading

Returns:

True if sysref counter incrementing

Return type:

dict of bool with an entry for each ADC

check_adc_sysref_setup_and_hold(adc_id=None, show_info=True)

Status of the ADC setup and hold monitor.

Returns True if no setup or hold error for a given ADC, else False.

Parameters:

• adc_id (int) – Specify which ADC, 0-15, None for all ADCs

• show_info (bool) – log description from ADC manual of current setup and hold.

Returns:

True if timing requirements OK

Return type:

dict of bool with an entry for each ADC

check_clock_manager_status(fpga_id=None, name=None)

Check status of named TPM clock manager cores (MMCM Core). Reports the status of each MMCM lock and its lock loss counter.

Example: ( current_status, historical_status_counter )

current_status: The current MMCM PLL lock status.

• True → MMCM PLL is currently locked as expected.

• False → MMCM PLL is not currently locked.

historical_status_counter: To detect transient loss of the PLL lock that occurs for less than 1 second, there is also the historical loss of lock counter. This counts the number of loss of lock events since the last query.

• 0 → No loss of PLL lock events have occured since the last query.

• N > 0 → N loss of PLL lock events have occured since the last query.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• name (str) – Specify name of clock manager (non case sensitive)

Returns:

(True, 0) if lock is up and no loss of lock

Return type:

dict of tuple with an entry for each FPGA and MMCM

check_clock_status(fpga_id=None, clock_name=None)

Status of TPM FPGA clocks.

If True, the clock is operating as expected. If False a clock overrun, underrun, glitch or stop error has been detected by the FPGA.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• clock_name (str) – Specify name of clock or None for all clocks. Input is non case sensitive. Options ‘jesd’, ‘ddr’, ‘udp’

Returns:

True when Status is OK, no errors

Return type:

bool

check_data_router_discarded_packets(fpga_id=None)

Number of station beam packets discarded by the data router.

The TPM supports sharing a single 40GbE QSFP connection between the two FPGAs, transmitting and receiving all UDP packets via a primary FPGA. The routing of all data to and from the FPGA-to-FPGA (F2F) interface and the active 40GbE UDP interface is managed by a component called the data router.

Example: [ rejected_packets, overflow_packets ]

rejected_packets: Packets that are discarded due to incorrect size.

• 0 → No packets were rejected since the last query.

• N > 0 → N packets were rejected since the last query.

overflow_packets: Packets that are discarded due to the UDP RX Input Selector FIFO being full.

• 0 → No packets overflows since the last query.

• N > 0 → N packet overflows since the last query.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

register values

Return type:

dict of list of counts with an entry for each FPGA

check_data_router_status(fpga_id=None)

Data router error flag status.

The TPM supports sharing a single 40GbE QSFP connection between the two FPGAs, transmitting and receiving all UDP packets via a primary FPGA. The routing of all data to and from the FPGA-to-FPGA (F2F) interface and the active 40GbE UDP interface is managed by a component called the data router.

The data router status is > 0 if any of the below errors are detected:

• The F2F to UDP Clock Domain Crossing FIFO (First-In, First-Out) is written

  when full.

• The UDP to F2F Clock Domain Crossing FIFO is written when full.

• The UDP TX Arbiter Packet FIFO for the primary FPGA’s staton beam is full.

• The UDP TX Arbiter Packet FIFO for the primary FPGA’s LMC data is stalled.

• The UDP TX Arbiter Packet FIFO for the secondary FPGA’s staton beam and LMC

  data is full.

• The UDP TX Payload FIFO is stalled.

• The UDP RX Input Selector FIFO is written when full.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

register values

Return type:

dict of int with an entry for each FPGA

check_ddr_initialisation(fpga_id=None)

Status of DDR4 initialization and calibration.

The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components.

If True, initialization and calibration are complete and the user can safely initiate read and write requests from the client interface.

See init_calib_complete in Xilinx UltraScale Architecture FPGAs Memory Interface Solutions.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

True if initialisation complete

Return type:

bool

check_ddr_parity_error_counter(fpga_id=None)

DDR parity error counter.

The TPM FPGA generates a basic parity which is used to detect errors in station beamformed samples read from the DDR memory during corner turning. This counter will increment for every error detected. Any errors suggests a hardware degredation of the TPM DDR4 SDRAM chips.

NOTE: For now, this is not full ECC (Error Correcting Code). A more complex parity alogorithm would be requires to provide automatic correction of parity errors as well as detection.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

counter values

Return type:

dict

check_ddr_reset_counter(fpga_id=None, show_result=True)

The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components.

To track any occurances of intermittent loss of the DDR, the FPGA increments a counter each time the FPGA detects a falling edge of the DDR user logic reset.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• show_result (bool) – prints error counts on logger

Returns:

counter values

Return type:

dict

check_dsp_latency_status(fpga_id=None)

Station signal processing chain latency status.

The final TPM in the station verifies the processing latency from ADC capture and time-tag to transmission in the final tile in the beamforming chain to CSP.

The DSP latency is calculated by measuring the difference between the SPEAD transmission timestamp in the station beamformer and the ADC sampling timestamp for the same packet.

The measured latency is compared to a threshold, typically 10 ms. The status is False if the latency exceeds the threshold. The current latency can be read using check_dsp_latency.

Check if the DSP latency has exceeded the allowed threshold. Returns Ture if the DSP latency is OK, else False.

NOTE: This should only be polled for the last tile in the station. For all other tiles the measured latency will be 0 ms so latency status will be True.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

True if DSP latency is OK, else False.

Return type:

bool

check_f2f_hard_errors()

Number of FPGA-to-FPGA link HARD errors as reported by the Xilinx Aurora core within the FPGA firmware.

See Xilinx Aurora 64B/66B v12.0 Product Guide.

Hard errors are those detected by monitoring the FPGA transceivers for hardware errors such as buffer overflow and loss of lock.

When a hard error occurs, the Aurora core automatically resets itself and attempts to re-initialize. In most cases, this permits re-establishing the Aurora 64B/66B channel when the hardware issue causing the hard error is resolved.

Returns:

hard_err register value

Return type:

int

check_f2f_pll_status(core_id=None, show_result=True)

Status of transciever quad QPLL which generates the high-speed serial clock required by the FPGA-to-FPGA link.

The current status and historical status of the FPGA-to-FPGA (F2F) QPLL.

Example: ( current_status, historical_status_counter )

current_status: The current QPLL lock status.

• True → The QPLL is locked as expected.

• False → The QPLL is not currently locked.

historical_status_counter: To detect transient loss of the QPLL lock that occurs for less than 1 second, there is also the historical loss of lock counter. This counts the number of loss of lock events since the last query.

• 0 → No loss of QPLL lock events have occured since the last query.

• N > 0 → N loss of QPLL lock events have occured since the last query.

Parameters:

• core_id (int) – Specify which F2F Core, 0, 1, or None for both cores

• show_result (bool) – prints error counts on logger

Returns:

(True, 0) if lock is up and no loss of lock

Return type:

dict of tuple with an entry for each core

check_f2f_soft_errors()

Number of FPGA-to-FPGA link SOFT errors as reported by the Xilinx Aurora core within the FPGA firmware.

See Xilinx Aurora 64B/66B v12.0 Product Guide.

Soft errors are those detected by the Aurora 64B/66B encoding method. These can be caused by equipment problems and channel noise.

Unlike hard errors, soft errors do not usually lead to a reset of the link.

Returns:

soft_err register value

Return type:

int

check_global_status_alarms()

Global alert flags for internal TPM BIOS checks against warning and alarm thresholds.

There is one flag for each of:

• I2C peripheral access status

• Temperature status

• Voltage status

• FPGA Single Error Mitigation (SEM) watchdog status

• MCU watchdog status

I2C_access_alm

• 0 → All peripherals reachable.

• 1 → Reserved.

• 2 → One or more peripherals unreachable.

temperature_alm

• 0 → All temperatures within range.

• 1 → One or more temperature warning threshold has been exceeded.

• 2 → One or more temperature alarm threhold has been exceeded. TPM FPGAs have been powered OFF.

voltage_alm

• 0 → All voltages within range.

• 1 → One or more voltage warning threshold has been exceeded.

• 2 → One or more voltage alarm threhold has been exceeded.

SEM_wd

• 0 → FPGA SEM working properly.

• 1 → Reserved.

• 2 → FPGA SEM watchdog expired.

MCU_wd

• 0 → MCU working properly.

• 1 → Reserved.

• 2 → MCU watchdog expired.

As reported above, when the temperature exceeds the alarm threshold, the TPM CPLD will take autonomous action and power down the TPM FPGAs.

These are live measurements of continuous (analog) quantities.

Returns:

alarm status dict

Return type:

dict

check_jesd_lane_error_counter(fpga_id=None, core_id=None)

JESD204 link error count per lane as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs.

To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes.

See Xilinx JESD204 v7.2 Product Guide.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• core_id (int) – Specify which JESD Core, 0, 1, or None for both cores

Returns:

dict of counts

Return type:

dict(int) with an entry for each FPGA, core and lane

check_jesd_lane_status(fpga_id=None, core_id=None)

TODO: Remove this monitoring point. This is simply a consolidated boolean form of the JESD204 link error counts above.

JESD204 link error summary per lane consolidated from the link error counts per lane as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs.

See Xilinx JESD204 v7.2 Product Guide.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• core_id (int) – Specify which JESD Core, 0, 1, or None for both cores

Returns:

True if all error counters are 0

Return type:

bool

check_jesd_link_status(fpga_id=None, core_id=None)

JESD204 lane synchronisation status as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs.

See Xilinx JESD204 v7.2 Product Guide.

JESD Sync Status is True if both of the below conditions are met:

• A SYSREF event has been captured.

• Link SYNC achieved.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• core_id (int) – Specify which JESD Core, 0, 1, or None for both cores

Returns:

True if a SYSREF event has been captured and link SYNC is achieved

Return type:

bool

check_jesd_qpll_status(fpga_id=None, show_result=True)

Status of transciever quad QPLL which generates the high-speed serial clock required by JESD204 links. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs.

Example: ( current_status, historical_status_counter )

current_status: The current QPLL lock status.

• True → The QPLL is locked as expected.

• False → The QPLL is not currently locked.

historical_status_counter: To detect transient loss of the QPLL lock that occurs for less than 1 second, there is also the historical loss of lock counter. This counts the number of loss of lock events since the last query.

• 0 → No loss of QPLL lock events have occured since the last query.

• N > 0 → N loss of QPLL lock events have occured since the last query.

NOTE: To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. The QPLL is shared between both JESD cores in each FPGA.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• show_result (bool) – prints error counts on logger

Returns:

(True, 0) if lock is up and no loss of lock

Return type:

dict of tuple with an entry for each FPGA

check_jesd_resync_counter(fpga_id=None, show_result=True)

A count of JESD resync events.

The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs.

To track any occurances of intermittent loss of the JESD SYNC, the FPGA increments a counter each time the FPGA detects a rising edge of the JESD SYNC.

NOTE: To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. The resync count is shared between both JESD cores in each FPGA, operating on the boolean AND of the JESD SYNC from both cores.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• show_result (bool) – prints error counts on logger

Returns:

counter values

Return type:

dict(int) with an entry for each FPGA

check_pps_status(fpga_id=None)

Status of the One Pulse-Per-Second (PPS) reference to the TPM. The PPS is used coherently time-tag data sampled by the ADC across multiple tiles.

PPS Status is True if both of the below conditions are met:

• The PPS is detected to be externally provided to the TPM from the subrack.

• The measured PPS period is exactly 1 second to a precision of 5 ns.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

True if PPS is detected and PPS period is as expected

Return type:

bool

check_station_beamformer_discarded_or_flagged_packet_count(fpga_id=None)

Number of discarded or flagged packets reportd by the final tile in the station beamformering chain. This is in units of packets received by the last tile in the station, travelling station beam packets that are \(\frac{1}{8}\) of a CSP packet.

When station beam flagging is disabled the number of discarded packets is reported. This will always be a multiple of 8 as a full CSP packet is discarded if it is not complete.

When station beam flagging is enabled, the number of substituted (flagged) packets is reported.

NOTE: This should only be polled for the last tile in the station. For all other tiles the values will be 0.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

counter values

Return type:

dict

check_station_beamformer_status(fpga_id=None)

Station beamformer error flag status.

Tiles in a station produce station beams by summing tile beams transmitted over a 40GbE network. Beams for sixteen dual polarisation antennas are summed into beams for 256 dual polarisation antennas.

The station beamformer status is False if any of the below errors are detected:

• The Core RAM FIFO buffer is read when empty.

• The Core RAM FIFO buffer is written when full (overflow).

• The SPEAD RAM FIFO buffer is read when empty.

• The SPEAD RAM FIFO buffer is written when full (overflow).

• The SPEAD packet FIFO buffer receives packets that are too short.

• The SPEAD packet FIFO buffer receives packets that are too long.

• The Corner Turner RAM FIFO buffer is read when empty.

• The Corner Turner RAM FIFO buffer is written when full (overflow).

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• show_result (bool) – prints error counts on logger

Returns:

True when Status is OK, no errors

Return type:

bool

check_tile_beamformer_status(fpga_id=None)

Tile beamformer error flag status.

The TPM FPGAs each channelize data for eight dual polarisation antennas. In addition to beam calibration and steering, the tile beamformer produces beams for sixteen dual polarisation antennas by exchanging data over the FPGA-to-FPGA interface. These error flags relate to this external interface of the tile beamformer.

The tile beamformer status is False if any of the below errors are detected:

• Packet boundaries for the data received over the FPGA-to-FPGA interface are

  not aligned with the local data.

• Local data FIFO buffer is written when full (overflow). Data from the

  FPGA-to-FPGA interface is arriving too slow or not at all.

• Local data FIFO buffer is read when empty. Data from the FPGA-to-FPGA

  interface is arriving too fast.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

True when Status is OK, no errors

Return type:

bool

check_udp_arp_table_status(fpga_id=None, show_result=True)

Check UDP 40GbE ARP Table has been populated correctly. The TPM FPGAs transmit data products as UDP packets to the Science Data Network (SDN) using 40GbE.

Confirms that all valid (populated) entries in the TPM 40GbE ARP table are resolved with MAC addresses.

NOTE: This is a non-destructive version of the method check_arp_table which is to be used during station initialise.

NOTE: ARP table entries for 40GbE QSFP connections that were disabled at initialise via the active_40g_ports_setting or qsfp_detection setting are skipped.

Parameters:

show_result (bool) – prints ARP table contents to logger

Returns:

True if all populated ARP table entries are also resolved

Return type:

bool

check_udp_bip_error_counter(fpga_id=None)

UDP 40GbE Bit Interleaved Parity (BIP) errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE.

RX BIP (Bit Interleaved Parity) errors indicate bit-level corruption detected at Layer-1 (Physical Layer) via parity checks, most commonly caused by physical transmission issues like signal degreated caused by faulty cables or transceivers.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

counter values

Return type:

dict of int with an entry for each FPGA and PHY lane

check_udp_crc_error_counter(fpga_id=None)

UDP 40GbE RX Cyclic Redundancy Check (CRC) errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE.

RX CRC (Cyclic Redundancy Check) errors indicate corrupted Ethernet frames detected at Layer-2 (Data Link Layer) via a checksum mismatch, most commonly caused by Layer-1 (Physical Layer) issues like faulty cables or transceivers.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

counter values

Return type:

dict

check_udp_decode_error_counter(fpga_id=None)

UDP 40GbE Physical Layer (PHY) 66B/64B decoding errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE.

PHY RX decode errors indicate failures in interpreting the incoming physical signal detected at Layer-1 (Physical Layer) due to invalid symbols or encoding violations, most commonly caused by severe signal integrity issues such as noise ot faulty cables or transceivers.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

counter values

Return type:

dict of int with an entry for each FPGA and PHY lane

check_udp_linkup_loss_counter(fpga_id=None, show_result=True)

UDP 40GbE link loss status. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE.

To track any occurances of intermittent loss of link-up, the FPGA increments a counter each time the FPGA detects the link is down by monitoring the UDP Physical Layer (PHY) virtual lanes are aligned signal.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• show_result (bool) – prints error counts on logger

Returns:

counter values

Return type:

dict

check_udp_status(fpga_id=None)

UDP 40GbE consolidated error status. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE.

UDP Status is True if all of the below conditions are met:

• The link is UP - the UDP Physical Layer (PHY) virtual lanes are aligned.

• There are no RX Cyclic Redundancy Check (CRC) errors.

• There are no RX Bit Interleave Parity (BIP) errors.

• There are no Physical Layer (PHY) 66B/64B RX decoding errors.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

True if link is up and error counters are 0

Return type:

bool

clear_ad9528_pll_status()

Resets the value in the AD9528 PLL lock loss counter to 0.

clear_ad9550_pll_status()

Resets the value in the AD9550 PLLs lock loss counter to 0.

clear_adc_pll_status(adc_id=None)

Resets the value in the ADC PLL lock loss sticky bit.

Parameters:

adc_id (int) – Specify which ADC, 0-15, None for all ADCs

clear_clock_manager_status(fpga_id=None, name=None)

Clear status of named TPM clock manager cores (MMCM Core). Used to reset MMCM lock loss counters.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• name (str) – Specify name of clock manager (non case sensitive)

clear_clock_status(fpga_id=None, clock_name=None)

Clear status of named TPM clocks Used to Clear error flags in FPGA Firmware Options ‘jesd’, ‘ddr’, ‘udp’ Input is non case sensitive An FPGA ID can be optionally specified to only clear status on one FPGA

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• clock_name (str) – Specify name of clock or None for all clocks

clear_data_router_status(fpga_id=None)

Reset data router error flags.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

clear_ddr_reset_counter(fpga_id=None)

Reset value of DDR user reset counter.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

clear_dsp_latency_status(fpga_id=None)

Clears the DSP latency status.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

clear_f2f_pll_lock_loss_counter(core_id=None)

Reset value of F2F PLL lock loss counter.

Parameters:

core_id (int) – Specify which F2F Core, 0, 1, or None for both cores

clear_global_status_alarms()

Clears global alert flags for internal TPM BIOS checks against warning and alarm thresholds.

clear_health_status(group=None)

Clears the values of all tile monitoring points. Only affects discrete monitoring points, has no affect on voltage and current measurements.

NOTE: each value is also reset independently at the end of each call to get_health_status(). This is necessary so that polling get_health_status returns only changes since that last poll.

TODO: This should be scripted to use the groups and clear methods specified in self.monitoring_point_lookup_dict. The group arg should also be changed to kwargs. Currently the clear_method entires are only used to clear following each call of get_health_status().

Parameters:

group (str) – Filter monitoring points to clear by group as defined in tpm_monitoring_point_lookup.

clear_jesd_error_counters(fpga_id=None)

Reset JESD error counters.

• JESD Error Counter

• JESD Resync Counter (shared between JESD cores)

• JESD QPLL Lock Loss Counter (shared between JESD cores)

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

clear_pps_status(fpga_id=None)

Clear PPS error flags.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

clear_station_beamformer_status(fpga_id=None)

Clear status of Station Beamformer error flags and counters. Including DDR parity error counter.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

clear_tile_beamformer_status(fpga_id=None)

Clear tile beamformer error flags.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

True when Status is OK, no errors

Return type:

bool

clear_udp_status(fpga_id=None)

Reset 40G error counters.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

define_monitoring_point_filter(path, override=True, **kwargs)

Create a custom filter to use with get_health_status(). Filters are any custom combination of keyword arguments.

This is intended to allow the upstream software to create custom groupings of monitoring points at run-time. Allowing each of these groups to be polled at different intervals.

As mentioned above in get_health_status(), one set of filters is pre-defined with the key group.

Example Filtering:

>>> tile.get_health_status(group='temperatures')

{
    "temperatures": {
        "board": 56.25,
        "FPGA0": 60.77,
        "FPGA1": 59.04,
        "ADC0": 60.33,
        "ADC1": 61.87,
        "ADC2": 62.82,
        "ADC3": 64.54,
        "ADC4": 64.76,
        "ADC5": 63.42,
        "ADC6": 63.36,
        "ADC7": 63.26,
        "ADC8": 64.42,
        "ADC9": 63.27,
        "ADC10": 63.74,
        "ADC11": 64.39,
        "ADC12": 64.49,
        "ADC13": 62.9,
        "ADC14": 62.24,
        "ADC15": 60.87
    }
}

Monitoring points to be included can be specified by a path, a string name produced from . delimited keys of the lookup dict. Some examples include io.udp_interface.crc_error_count', 'io.udp_interface', 'timing' or 'io'. All available options are returned from all_monitoring_categories() see below.

Example 1, to create and use a filter to poll only the TPM IO’s UDP interface CRC error counters for both FPGAs. The path for these would be io.udp_interface.crc_error_count.FPGA0 and io.udp_interface.crc_error_count.FPGA1 so a filter can be created using their exclusive common parent io.udp_interface.crc_error_count:

>>> tile.define_monitoring_point_filter('io.udp_interface.crc_error_count', new_custom_key=87)
[INFO]: Setting new_custom_key for io.udp_interface.crc_error_count.FPGA0 to 87.
[INFO]: Setting new_custom_key for io.udp_interface.crc_error_count.FPGA1 to 87.

>>> tile.get_health_status(new_custom_key=87)
{
  "io": {
    "udp_interface": {
      "crc_error_count": {
        "FPGA0": 0,
        "FPGA1": 0
      }
    }
  }
}

Any keyword argument combination can be used, here an arbitrary new_custom_key=87 has been used.

Example 2, to create and use a filter for only the TPM DDR termination voltages and DDR interface reset counter. The path for these would be 'voltages.VM_DDR0_VTT', 'voltages.VM_DDR1_VTT', 'io.ddr_interface.reset_counter.FPGA0' and 'io.ddr_interface.reset_counter.FPGA1' so a filter can be created using 'voltages.VM_DDR0_VTT', 'voltages.VM_DDR1_VTT' and 'io.ddr_interface.reset_counter':

>>> tile.define_monitoring_point_filter('voltages.VM_DDR0_VTT', second_custom_key='ddr')
[INFO]: Setting second_custom_key for voltages.VM_DDR0_VTT to ddr.

>>> tile.define_monitoring_point_filter('voltages.VM_DDR1_VTT', second_custom_key='ddr')
[INFO]: Setting second_custom_key for voltages.VM_DDR1_VTT to ddr.

>>> tile.define_monitoring_point_filter('io.ddr_interface.reset_counter', second_custom_key='ddr')
[INFO]: Setting second_custom_key for io.ddr_interface.reset_counter.FPGA0 to ddr.
[INFO]: Setting second_custom_key for io.ddr_interface.reset_counter.FPGA1 to ddr.

>>> tile.get_health_status(second_custom_key='ddr')
{
  "voltages": {
    "VM_DDR0_VTT": 0.604,
    "VM_DDR1_VTT": 0.605
  },
  "io": {
    "ddr_interface": {
      "reset_counter": {
        "FPGA0": 0,
        "FPGA1": 0
      }
    }
  }
}

Example 3, to create and use a custom filter called rate with string values:

>>> tile.define_monitoring_point_filter('alarms', rate="fast")
[INFO]: Setting rate for alarms to fast.

>>> tile.define_monitoring_point_filter('voltages', rate="slow")
[INFO]: Setting rate for voltages.MGT_AVCC to slow.
[INFO]: Setting rate for voltages.MGT_AVTT to slow.
[INFO]: Setting rate for voltages.SW_AVDD1 to slow.
[INFO]: Setting rate for voltages.SW_AVDD2 to slow.
[INFO]: Setting rate for voltages.AVDD3 to slow.
[INFO]: Setting rate for voltages.MAN_1V2 to slow.
[INFO]: Setting rate for voltages.DDR0_VREF to slow.
[INFO]: Setting rate for voltages.DDR1_VREF to slow.
[INFO]: Setting rate for voltages.VM_DRVDD to slow.
[INFO]: Setting rate for voltages.VIN to slow.
[INFO]: Setting rate for voltages.MON_3V3 to slow.
[INFO]: Setting rate for voltages.MON_1V8 to slow.
[INFO]: Setting rate for voltages.MON_5V0 to slow.
[INFO]: Setting rate for voltages.VM_AGP0 to slow.
[INFO]: Setting rate for voltages.VM_AGP1 to slow.
[INFO]: Setting rate for voltages.VM_AGP2 to slow.
[INFO]: Setting rate for voltages.VM_AGP3 to slow.
[INFO]: Setting rate for voltages.VM_CLK0B to slow.
[INFO]: Setting rate for voltages.VM_DDR0_VTT to slow.
[INFO]: Setting rate for voltages.VM_FE0 to slow.
[INFO]: Setting rate for voltages.VM_MGT0_AUX to slow.
[INFO]: Setting rate for voltages.VM_PLL to slow.
[INFO]: Setting rate for voltages.VM_AGP4 to slow.
[INFO]: Setting rate for voltages.VM_AGP5 to slow.
[INFO]: Setting rate for voltages.VM_AGP6 to slow.
[INFO]: Setting rate for voltages.VM_AGP7 to slow.
[INFO]: Setting rate for voltages.VM_CLK1B to slow.
[INFO]: Setting rate for voltages.VM_DDR1_VDD to slow.
[INFO]: Setting rate for voltages.VM_DDR1_VTT to slow.
[INFO]: Setting rate for voltages.VM_DVDD to slow.
[INFO]: Setting rate for voltages.VM_FE1 to slow.
[INFO]: Setting rate for voltages.VM_MGT1_AUX to slow.
[INFO]: Setting rate for voltages.VM_SW_AMP to slow.

>>> tile.get_health_status(rate="fast")
{
  "alarms": {
    "I2C_access_alm": 0,
    "temperature_alm": 0,
    "voltage_alm": 0,
    "SEM_wd": 0,
    "MCU_wd": 0
  }
}

>>> tile.get_health_status(rate="slow")
{
  "voltages": {
    "MGT_AVCC": 0.889,
    "MGT_AVTT": 1.15,
    "SW_AVDD1": 1.082,
    "SW_AVDD2": 2.295,
    "AVDD3": 2.499,
    "MAN_1V2": 1.202,
    "DDR0_VREF": 0.595,
    "DDR1_VREF": 0.595,
    "VM_DRVDD": 1.804,
    "VIN": 11.922,
    "MON_3V3": 3.691,
    "MON_1V8": 2.02,
    "MON_5V0": 4.944,
    "VM_AGP0": 0.916,
    "VM_AGP1": 0.916,
    "VM_AGP2": 0.919,
    "VM_AGP3": 0.917,
    "VM_CLK0B": 3.309,
    "VM_DDR0_VTT": 0.605,
    "VM_FE0": 3.525,
    "VM_MGT0_AUX": 1.783,
    "VM_PLL": 3.307,
    "VM_AGP4": 0.917,
    "VM_AGP5": 0.915,
    "VM_AGP6": 0.92,
    "VM_AGP7": 0.915,
    "VM_CLK1B": 3.309,
    "VM_DDR1_VDD": 1.196,
    "VM_DDR1_VTT": 0.604,
    "VM_DVDD": 1.096,
    "VM_FE1": 3.524,
    "VM_MGT1_AUX": 1.8,
    "VM_SW_AMP": 3.522
  }
}

>>> tile.define_monitoring_point_filter('alarms', rate="slow", override=False)
[INFO]: Appending rate for alarms with slow.
[INFO]: rate for alarms now ['slow', 'fast'].

>>> tile.get_health_status(rate="slow")
{
  "voltages": {
    "MGT_AVCC": 0.89,
    "MGT_AVTT": 1.15,
    "SW_AVDD1": 1.081,
    "SW_AVDD2": 2.295,
    "AVDD3": 2.499,
    "MAN_1V2": 1.202,
    "DDR0_VREF": 0.595,
    "DDR1_VREF": 0.595,
    "VM_DRVDD": 1.812,
    "VIN": 11.891,
    "MON_3V3": 3.652,
    "MON_1V8": 2.013,
    "MON_5V0": 4.929,
    "VM_AGP0": 0.916,
    "VM_AGP1": 0.915,
    "VM_AGP2": 0.918,
    "VM_AGP3": 0.916,
    "VM_CLK0B": 3.305,
    "VM_DDR0_VTT": 0.604,
    "VM_FE0": 3.523,
    "VM_MGT0_AUX": 1.782,
    "VM_PLL": 3.304,
    "VM_AGP4": 0.917,
    "VM_AGP5": 0.915,
    "VM_AGP6": 0.92,
    "VM_AGP7": 0.915,
    "VM_CLK1B": 3.309,
    "VM_DDR1_VDD": 1.195,
    "VM_DDR1_VTT": 0.605,
    "VM_DVDD": 1.096,
    "VM_FE1": 3.525,
    "VM_MGT1_AUX": 1.8,
    "VM_SW_AMP": 3.522
  },
  "alarms": {
    "I2C_access_alm": 0,
    "temperature_alm": 0,
    "voltage_alm": 0,
    "SEM_wd": 0,
    "MCU_wd": 0
  }
}

The above example defines a rate filter which allows alarm status to be read with rate="fast" and additionally alarm status and voltages to be read with rate="slow". By default, the provided value for a keyword argument will override any existing filter defined. To instead append values, use override=False.

Parameters:

• path (str) – Monitoring point path (e.g. 'io.udp_interface.crc_error_count', 'io.udp_interface', 'timing', 'io')

• override (bool) – Overrides all values for the provided keyword if True, if False, the value is appended to any previous values for that key.

• kwargs (dict (values can be any immutable type or list of)) – keyword arguments to filter health status fetched

disable_clock_monitoring(fpga_id=None, clock_name=None)

Disable clock monitoring of named TPM clocks Options ‘jesd’, ‘ddr’, ‘udp’ Input is non case sensitive An FPGA ID can be optionally specified to only disable monitoring on one FPGA

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• clock_name (str) – Specify name of clock or None for all clocks

enable_clock_monitoring(fpga_id=None, clock_name=None)

Enable clock monitoring of named TPM clocks Options ‘jesd’, ‘ddr’, ‘udp’ Input is non case sensitive An FPGA ID can be optionally specified to only enable monitoring on one FPGA

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• clock_name (str) – Specify name of clock or None for all clocks

enable_health_monitoring()

Some monitoring points must be enabled in firmware duirng tile initialise. Currently this is only affects the monitoring of clocks.

fpga_gen(fpga_id)

get_adc_temperature(adc_id=None)

ADC temperature. This is the temperature as reported by the temperature diode of the AD9695 ADC. Measurement is a float in °C.

When an ADC temperature measurment is taken, the ADC is configured to output the temperature diode voltage to a pin which is sampled by the on-chip Xilinx System Monitor core within the FPGA firmware.

Parameters:

adc_id (int) – Specify which ADC, 0-15, None for all ADCs

Returns:

ADC temperature

Return type:

dict

get_available_clock_managers()

get_available_clocks_to_monitor()

Returns:

list of clock names available to be monitored

Return type:

list of str

get_available_currents(fpga_id=None)

Get list of available current measurements for TPM.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

TPM current names

Return type:

list

get_available_voltages(fpga_id=None)

Get list of available voltage measurements for TPM.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

TPM voltage names

Return type:

list

get_current(fpga_id=None, current_name=None)

TPM current measurement.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• current_name (str) – Specify name of current, None for all currents

Returns:

TPM currents

Return type:

dict

get_fpga_temperature(fpga_id=None)

FPGA temperature. This is the temperature as reported by the on-chip Xilinx System Monitor core within the FPGA firmware. Measurement is a float in °C.

See Xilinx UltraScale Architecture System Monitor User Guide.

Parameters:

fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

Returns:

FPGA temperature

Return type:

dict

get_health_status(**kwargs)

Returns the current value of TPM monitoring points. If not arguments are given, the current value of all monitoring points if returned.

It is possible to filter the monitoring points requested using keyword arguments. Monitoring points can be categoried using keyword arguments using the define_monitoring_point_filter() method. By default one filter is pre-defined

group

• temperatures

• voltages

• currents

• alarms

• adcs

• timing

  • clocks

  • clock_managers

  • pps

  • pll

• io

  • jesd_interface

  • ddr_interface

  • f2f_interface

  • udp_interface

  • data_router

• dsp

  • tile_beamf

  • station_beamf

  • max_broadband_rfi

Example:

>>> tile.get_health_status()

{
  "temperatures": {
    "board": 37.5,
    "FPGA0": 45.0,
    "FPGA1": 45.0,
    "ADC0": 45.0,
    "ADC1": 45.0,
    "ADC2": 45.0,
    "ADC3": 45.0,
    "ADC4": 45.0,
    "ADC5": 45.0,
    "ADC6": 45.0,
    "ADC7": 45.0,
    "ADC8": 45.0,
    "ADC9": 45.0,
    "ADC10": 45.0,
    "ADC11": 45.0,
    "ADC12": 45.0,
    "ADC13": 45.0,
    "ADC14": 45.0,
    "ADC15": 45.0
  },
  "voltages": {
    "MGT_AVCC": 0.89,
    "MGT_AVTT": 1.18,
    "SW_AVDD1": 1.09,
    "SW_AVDD2": 2.3,
    "AVDD3": 2.5,
    "MAN_1V2": 1.2,
    "DDR0_VREF": 0.6,
    "DDR1_VREF": 0.6,
    "VM_DRVDD": 1.8,
    "VIN": 12.0,
    "MON_3V3": 3.69,
    "MON_1V8": 2.0,
    "MON_5V0": 5.0,
    "VM_AGP0": 0.92,
    "VM_AGP1": 0.92,
    "VM_AGP2": 0.92,
    "VM_AGP3": 0.92,
    "VM_CLK0B": 3.3,
    "VM_DDR0_VTT": 0.6,
    "VM_FE0": 3.5,
    "VM_MGT0_AUX": 1.8,
    "VM_PLL": 3.3,
    "VM_AGP4": 0.92,
    "VM_AGP5": 0.92,
    "VM_AGP6": 0.92,
    "VM_AGP7": 0.92,
    "VM_CLK1B": 3.3,
    "VM_DDR1_VDD": 1.2,
    "VM_DDR1_VTT": 0.6,
    "VM_DVDD": 1.1,
    "VM_FE1": 3.5,
    "VM_MGT1_AUX": 1.8,
    "VM_SW_AMP": 3.5
  },
  "currents": {
    "FE0_mVA": 1.31,
    "FE1_mVA": 1.31
  },
  "alarms": {
    "I2C_access_alm": 0,
    "temperature_alm": 0,
    "voltage_alm": 0,
    "SEM_wd": 0,
    "MCU_wd": 0
  },
  "adcs": {
    "pll_status": {
      "ADC0": [
        true,
        true
      ],
      "ADC1": [
        true,
        true
      ],
      "ADC2": [
        true,
        true
      ],
      "ADC3": [
        true,
        true
      ],
      "ADC4": [
        true,
        true
      ],
      "ADC5": [
        true,
        true
      ],
      "ADC6": [
        true,
        true
      ],
      "ADC7": [
        true,
        true
      ],
      "ADC8": [
        true,
        true
      ],
      "ADC9": [
        true,
        true
      ],
      "ADC10": [
        true,
        true
      ],
      "ADC11": [
        true,
        true
      ],
      "ADC12": [
        true,
        true
      ],
      "ADC13": [
        true,
        true
      ],
      "ADC14": [
        true,
        true
      ],
      "ADC15": [
        true,
        true
      ]
    },
    "sysref_timing_requirements": {
      "ADC0": true,
      "ADC1": true,
      "ADC2": true,
      "ADC3": true,
      "ADC4": true,
      "ADC5": true,
      "ADC6": true,
      "ADC7": true,
      "ADC8": true,
      "ADC9": true,
      "ADC10": true,
      "ADC11": true,
      "ADC12": true,
      "ADC13": true,
      "ADC14": true,
      "ADC15": true
    },
    "sysref_counter": {
      "ADC0": true,
      "ADC1": true,
      "ADC2": true,
      "ADC3": true,
      "ADC4": true,
      "ADC5": true,
      "ADC6": true,
      "ADC7": true,
      "ADC8": true,
      "ADC9": true,
      "ADC10": true,
      "ADC11": true,
      "ADC12": true,
      "ADC13": true,
      "ADC14": true,
      "ADC15": true
    }
  },
  "timing": {
    "clocks": {
      "FPGA0": {
        "JESD": true,
        "DDR": true,
        "UDP": true
      },
      "FPGA1": {
        "JESD": true,
        "DDR": true,
        "UDP": true
      }
    },
    "clock_managers": {
      "FPGA0": {
        "C2C_MMCM": [
          true,
          0
        ],
        "JESD_MMCM": [
          true,
          0
        ],
        "DSP_MMCM": [
          true,
          0
        ]
      },
      "FPGA1": {
        "C2C_MMCM": [
          true,
          0
        ],
        "JESD_MMCM": [
          true,
          0
        ],
        "DSP_MMCM": [
          true,
          0
        ]
      }
    },
    "timestamp": {
      "FPGA0": 15,
      "FPGA1": 15
    },
    "pps": {
      "status": true
    },
    "pll": [
      true,
      0
    ],
    "pll_40g": [
      true,
      0
    ]
  },
  "io": {
    "jesd_interface": {
      "link_status": true,
      "lane_error_count": {
        "FPGA0": {
          "Core0": {
            "lane0": 0,
            "lane1": 0,
            "lane2": 0,
            "lane3": 0,
            "lane4": 0,
            "lane5": 0,
            "lane6": 0,
            "lane7": 0
          },
          "Core1": {
            "lane0": 0,
            "lane1": 0,
            "lane2": 0,
            "lane3": 0,
            "lane4": 0,
            "lane5": 0,
            "lane6": 0,
            "lane7": 0
          }
        },
        "FPGA1": {
          "Core0": {
            "lane0": 0,
            "lane1": 0,
            "lane2": 0,
            "lane3": 0,
            "lane4": 0,
            "lane5": 0,
            "lane6": 0,
            "lane7": 0
          },
          "Core1": {
            "lane0": 0,
            "lane1": 0,
            "lane2": 0,
            "lane3": 0,
            "lane4": 0,
            "lane5": 0,
            "lane6": 0,
            "lane7": 0
          }
        }
      },
      "lane_status": true,
      "resync_count": {
        "FPGA0": 0,
        "FPGA1": 0
      },
      "qpll_status": {
        "FPGA0": [
          true,
          0
        ],
        "FPGA1": [
          true,
          0
        ]
      }
    },
    "ddr_interface": {
      "initialisation": true,
      "reset_counter": {
        "FPGA0": 0,
        "FPGA1": 0
      },
      "rd_cnt": {
        "FPGA0": 15,
        "FPGA1": 15
      },
      "wr_cnt": {
        "FPGA0": 15,
        "FPGA1": 15
      },
      "rd_dat_cnt": {
        "FPGA0": 15,
        "FPGA1": 15
      }
    },
    "f2f_interface": {
      "pll_status": [
        true,
        0
      ],
      "soft_error": 0,
      "hard_error": 0
    },
    "udp_interface": {
      "arp": true,
      "status": true,
      "crc_error_count": {
        "FPGA0": 0,
        "FPGA1": 0
      },
      "bip_error_count": {
        "FPGA0": {
          "lane0": 0,
          "lane1": 0,
          "lane2": 0,
          "lane3": 0
        },
        "FPGA1": {
          "lane0": 0,
          "lane1": 0,
          "lane2": 0,
          "lane3": 0
        }
      },
      "decode_error_count": {
        "FPGA0": {
          "lane0": 0,
          "lane1": 0,
          "lane2": 0,
          "lane3": 0
        },
        "FPGA1": {
          "lane0": 0,
          "lane1": 0,
          "lane2": 0,
          "lane3": 0
        }
      },
      "linkup_loss_count": {
        "FPGA0": 0,
        "FPGA1": 0
      }
    },
    "data_router": {
      "status": {
        "FPGA0": 0,
        "FPGA1": 0
      },
      "discarded_packets": {
        "FPGA0": [
          0,
          0
        ],
        "FPGA1": [
          0,
          0
        ]
      }
    }
  },
  "dsp": {
    "tile_beamf": true,
    "station_beamf": {
      "status": true,
      "discarded_or_flagged_packet_count": {
        "FPGA0": 0,
        "FPGA1": 0
      },
      "ddr_parity_error_count": {
        "FPGA0": 0,
        "FPGA1": 0
      },
      "dsp_latency_error": true
    },
    "max_broadband_rfi": 32767
  }
}

Example Filtering:

>>> tile.get_health_status(group='temperatures')

{
    "temperatures": {
        "board": 56.25,
        "FPGA0": 60.77,
        "FPGA1": 59.04,
        "ADC0": 60.33,
        "ADC1": 61.87,
        "ADC2": 62.82,
        "ADC3": 64.54,
        "ADC4": 64.76,
        "ADC5": 63.42,
        "ADC6": 63.36,
        "ADC7": 63.26,
        "ADC8": 64.42,
        "ADC9": 63.27,
        "ADC10": 63.74,
        "ADC11": 64.39,
        "ADC12": 64.49,
        "ADC13": 62.9,
        "ADC14": 62.24,
        "ADC15": 60.87
    }
}

Some monitoring points reflect a live measurement or state, for example, voltages, temperatures and ARP status. These are either continuous readings or quantities that update slow enough they can be reliably read from software without being cached in firmware. Other monitoring points including most FPGA IO and DSP error counters are cached in firmware between calls to get_health_status. In these cases results are fetched and then the cached value is also cleared. The result is that polling get_health_status returns only changes since that last poll. Below is a high level summary of which monitoring points are cleared on each poll.

Summary of which monitoring points are cleared when read

• Temperatures

  • Board ❌

  • FPGA0 ❌

  • FPGA1 ❌

  • ADC0 ❌

  • ADC1 ❌

  • ADC2 ❌

  • ADC3 ❌

  • ADC4 ❌

  • ADC5 ❌

  • ADC6 ❌

  • ADC7 ❌

  • ADC8 ❌

  • ADC9 ❌

  • ADC10 ❌

  • ADC11 ❌

  • ADC12 ❌

  • ADC13 ❌

  • ADC14 ❌

  • ADC15 ❌

• Voltages

  • MGT AVCC ❌

  • MGT AVTT ❌

  • SW AVDD1 ❌

  • SW AVDD2 ❌

  • AVDD3 ❌

  • MAN 1V2 ❌

  • DDR0 VREF ❌

  • DDR1 VREF ❌

  • VM DRVDD ❌

  • VIN ❌

  • MON 3V3 ❌

  • MON 1V8 ❌

  • MON 5V0 ❌

  • VM AGP0 ❌

  • VM AGP1 ❌

  • VM AGP2 ❌

  • VM AGP3 ❌

  • VM CLK0B ❌

  • VM DDR0 VTT ❌

  • VM FE0 ❌

  • VM MGT0 AUX ❌

  • VM PLL ❌

  • VM AGP4 ❌

  • VM AGP5 ❌

  • VM AGP6 ❌

  • VM AGP7 ❌

  • VM CLK1B ❌

  • VM DDR1 VDD ❌

  • VM DDR1 VTT ❌

  • VM DVDD ❌

  • VM FE1 ❌

  • VM MGT1 AUX ❌

  • VM SW AMP ❌

• Currents

  • FE0 MVA ❌

  • FE1 MVA ❌

• Alarms ✅

• ADCs

  • PLL Status

    • ADC0 ✅

    • ADC1 ✅

    • ADC2 ✅

    • ADC3 ✅

    • ADC4 ✅

    • ADC5 ✅

    • ADC6 ✅

    • ADC7 ✅

    • ADC8 ✅

    • ADC9 ✅

    • ADC10 ✅

    • ADC11 ✅

    • ADC12 ✅

    • ADC13 ✅

    • ADC14 ✅

    • ADC15 ✅

  • SYSREF Timing Requirements

    • ADC0 ❌

    • ADC1 ❌

    • ADC2 ❌

    • ADC3 ❌

    • ADC4 ❌

    • ADC5 ❌

    • ADC6 ❌

    • ADC7 ❌

    • ADC8 ❌

    • ADC9 ❌

    • ADC10 ❌

    • ADC11 ❌

    • ADC12 ❌

    • ADC13 ❌

    • ADC14 ❌

    • ADC15 ❌

  • SYSREF Counter

    • ADC0 ❌

    • ADC1 ❌

    • ADC2 ❌

    • ADC3 ❌

    • ADC4 ❌

    • ADC5 ❌

    • ADC6 ❌

    • ADC7 ❌

    • ADC8 ❌

    • ADC9 ❌

    • ADC10 ❌

    • ADC11 ❌

    • ADC12 ❌

    • ADC13 ❌

    • ADC14 ❌

    • ADC15 ❌

• Timing

  • Clocks

    • FPGA0

      • JESD ✅

      • DDR ✅

      • UDP ✅

    • FPGA1

      • JESD ✅

      • DDR ✅

      • UDP ✅

  • Clock Managers

    • FPGA0

      • C2C MMCM ✅

      • JESD MMCM ✅

      • DSP MMCM ✅

    • FPGA1

      • C2C MMCM ✅

      • JESD MMCM ✅

      • DSP MMCM ✅

  • Timestamp

    • FPGA0 ❌

    • FPGA1 ❌

  • PPS

    • Status ✅

  • PLL ✅

  • PLL 40G ✅

• IO

  • JESD Interface

    • Link Status ❌

    • Lane Error Count

      • FPGA0

        • Core0 ✅

        • Core1 ✅

      • FPGA1

        • Core0 ✅

        • Core1 ✅

    • Lane Status ✅

    • Resync Count

      • FPGA0 ✅

      • FPGA1 ✅

    • QPLL Status

      • FPGA0 ✅

      • FPGA1 ✅

  • DDR Interface

    • Initialisation ❌

    • Reset Counter

      • FPGA0 ✅

      • FPGA1 ✅

    • Rd Cnt

      • FPGA0 ❌

      • FPGA1 ❌

    • Wr Cnt

      • FPGA0 ❌

      • FPGA1 ❌

    • Rd Dat Cnt

      • FPGA0 ❌

      • FPGA1 ❌

  • F2F Interface

    • PLL Status ✅

    • Soft Error ❌

    • Hard Error ❌

  • UDP Interface

    • ARP ❌

    • Status ✅

    • CRC Error Count

      • FPGA0 ✅

      • FPGA1 ✅

    • BIP Error Count

      • FPGA0 ✅

      • FPGA1 ✅

    • Decode Error Count

      • FPGA0 ✅

      • FPGA1 ✅

    • Linkup Loss Count

      • FPGA0 ✅

      • FPGA1 ✅

  • Data Router

    • Status ✅

    • Discarded Packets ✅

• DSP

  • Tile Beamformer ✅

  • Station Beamformer

    • Status ✅

    • Discarded Or Flagged Packet Count ✅

    • DDR Parity Error Count ✅

    • DSP Latency Error ✅

  • Max Broadband RFI ✅

See the full documentation provided on each monitoring point to find a rationale for all those which are not cleared.

Parameters:

kwargs (dict) – keyword arguments to filter health status fetched

Returns:

Health status

Return type:

dict

get_tpm_temperature_thresholds()

Return a dictionary of temperature thresholds.

return structure looks like:

{ "board_warning_threshold": max, "board_alarm_threshold"  : max, "fpga1_warning_threshold": max, "fpga1_alarm_threshold": max, "fpga2_warning_threshold": max, "fpga2_alarm_threshold": max, }

Returns:

A dictionary containing the temperature thresholds.

Return type:

dict

get_voltage(fpga_id=None, voltage_name=None)

TPM voltage measurement.

Parameters:

• fpga_id (int) – Specify which FPGA, 0, 1, or None for both FPGAs

• voltage_name (str) – Specify name of voltage, None for all voltages

Returns:

TPM voltages

Return type:

dict

init_health_monitoring()

Method to load monitoring point lookup dict into attribute.

TPM monitoring point format and lookup loaded from: tpm_monitoring_point_lookup.py

inject_ddr_parity_error(fpga_id=None)

set_tpm_temperature_thresholds(max_board_alarm_threshold=None, max_fpga1_alarm_threshold=None, max_fpga2_alarm_threshold=None)

Set the temperature thresholds.

NOTE: Warning this method can configure the shutdown temperature of components and must be used with care. This method is capped to a maximum of 50 (unit: Degree Celsius). And is ONLY supported in tpm1_6.

Parameters:

• max_board_alarm_threshold – The maximum alarm thresholds for the board (unit: Degree Celsius)

• max_fpga1_alarm_threshold – The maximum alarm thresholds for the fpga1 (unit: Degree Celsius)

• max_fpga2_alarm_threshold – The maximum alarm thresholds for the fpga2 (unit: Degree Celsius)

Raises:

ValueError – If attempting to set a value outside the specified limit 20-50.

Return type:

None