DSP

Tile Beamformer

Description:

Tile beamformer error flag status.

The TPM FPGAs each channelize data for eight dual polarisation antennas. In addition to beam calibration and steering, the tile beamformer produces beams for sixteen dual polarisation antennas by exchanging data over the FPGA-to-FPGA interface. These error flags relate to this external interface of the tile beamformer.

The tile beamformer status is False if any of the below errors are detected:

Packet boundaries for the data received over the FPGA-to-FPGA interface are not aligned with the local data.
Local data FIFO buffer is written when full (overflow). Data from the FPGA-to-FPGA interface is arriving too slow or not at all.
Local data FIFO buffer is read when empty. Data from the FPGA-to-FPGA interface is arriving too fast.

Groups: dsp, tile_beamf
Reported By: TPM FPGAs
Expected: True
Cleared When Read: Yes

Developer info

Tile Method: check_tile_beamformer_status
- Arguments:
  - fpga_id (int): Specify which FPGA, 0, 1, or None for both FPGAs
- Returns: True when Status is OK, no errors (bool)
Tile Method to Clear: clear_tile_beamformer_status

Station Beamformer

Status

Description:

Station beamformer error flag status.

Tiles in a station produce station beams by summing tile beams transmitted over a 40GbE network. Beams for sixteen dual polarisation antennas are summed into beams for 256 dual polarisation antennas.

The station beamformer status is False if any of the below errors are detected:

The Core RAM FIFO buffer is read when empty.
The Core RAM FIFO buffer is written when full (overflow).
The SPEAD RAM FIFO buffer is read when empty.
The SPEAD RAM FIFO buffer is written when full (overflow).
The SPEAD packet FIFO buffer receives packets that are too short.
The SPEAD packet FIFO buffer receives packets that are too long.
The Corner Turner RAM FIFO buffer is read when empty.
The Corner Turner RAM FIFO buffer is written when full (overflow).

Groups: dsp, station_beamf
Reported By: TPM FPGAs
Expected: True
Cleared When Read: Yes

Developer info

Tile Method: check_station_beamformer_status
- Arguments:
  - fpga_id (int): Specify which FPGA, 0, 1, or None for both FPGAs
  - show_result (bool): prints error counts on logger
- Returns: True when Status is OK, no errors (bool)
Tile Method to Clear: clear_station_beamformer_status

Discarded Or Flagged Packet Count

Description:

Number of discarded or flagged packets reportd by the final tile in the station beamformering chain. This is in units of packets received by the last tile in the station, travelling station beam packets that are \( \frac{1}{8} \) of a CSP packet.

When station beam flagging is disabled the number of discarded packets is reported. This will always be a multiple of 8 as a full CSP packet is discarded if it is not complete.

When station beam flagging is enabled, the number of substituted (flagged) packets is reported.

NOTE: This should only be polled for the last tile in the station. For all other tiles the values will be 0.

Groups: dsp, station_beamf
Reported By: TPM FPGAs
Expected: {'FPGA0': 0, 'FPGA1': 0}
Cleared When Read: Yes

Developer info

Tile Method: check_station_beamformer_discarded_or_flagged_packet_count
- Arguments:
  - fpga_id (int): Specify which FPGA, 0, 1, or None for both FPGAs
- Returns: counter values (dict)
Tile Method to Clear: clear_station_beamformer_status

DDR Parity Error Count

Description:

DDR parity error counter.

The TPM FPGA generates a basic parity which is used to detect errors in station beamformed samples read from the DDR memory during corner turning. This counter will increment for every error detected. Any errors suggests a hardware degredation of the TPM DDR4 SDRAM chips.

NOTE: For now, this is not full ECC (Error Correcting Code). A more complex parity alogorithm would be requires to provide automatic correction of parity errors as well as detection.

Groups: dsp, station_beamf
Reported By: TPM FPGAs
Expected: {'FPGA0': 0, 'FPGA1': 0}
Cleared When Read: Yes

Developer info

Tile Method: check_ddr_parity_error_counter
- Arguments:
  - fpga_id (int): Specify which FPGA, 0, 1, or None for both FPGAs
- Returns: counter values (dict)
Tile Method to Clear: clear_station_beamformer_status

DSP Latency Error

Description:

Station signal processing chain latency status.

The final TPM in the station verifies the processing latency from ADC capture and time-tag to transmission in the final tile in the beamforming chain to CSP.

The DSP latency is calculated by measuring the difference between the SPEAD transmission timestamp in the station beamformer and the ADC sampling timestamp for the same packet.

The measured latency is compared to a threshold, typically 10 ms. The status is False if the latency exceeds the threshold. The current latency can be read using check_dsp_latency.

Check if the DSP latency has exceeded the allowed threshold. Returns Ture if the DSP latency is OK, else False.

NOTE: This should only be polled for the last tile in the station. For all other tiles the measured latency will be 0 ms so latency status will be True.

Groups: dsp, station_beamf
Reported By: TPM FPGAs
Expected: True
Cleared When Read: Yes

Developer info

Tile Method: check_dsp_latency_status
- Arguments:
  - fpga_id (int): Specify which FPGA, 0, 1, or None for both FPGAs
- Returns: True if DSP latency is OK, else False. (bool)
Tile Method to Clear: clear_dsp_latency_status

Max Broadband RFI

Description:

The maximum number of ADC frames containing broadband RFI across all antennas.

A count is maintained per dual polarisation antenna (and associated ADC) of broadband RFI-affected frames. The value returned is the highest of these counters.

A count of ADC frames containing broadband RFI for all dual polarisation antennas can be read using read_broadband_rfi.

Groups: dsp, max_broadband_rfi
Reported By: TPM FPGAs
Expected: up to 65535
Cleared When Read: Yes

Developer info

Tile Method: max_broadband_rfi
- Returns: Maximum number of ADC frames containing broadband RFI (int)
Tile Method to Clear: clear_broadband_rfi