pattern_generator

Overview

can produce pattern data for jesd (ADC), and for the LMC channelizer, beamformer, intergrated channelizer, intergrated beamformer data

Python Class & Methods Index

class pyfabil.plugins.tpm.pattern_generator.TpmPatternGenerator(board, **kwargs)

Pattern generator

channelize_pattern(pattern)

Change the frequency channel order to match che channelizer output :param pattern: pattern buffer, frequency channel in increasing order

check_stage(stage)

clean_up()

Perform cleanup :return: Success

clear_signal_adder(stage)

Clear signal adder. Set to zero the signal adder of each signal. :param stage: stage where write clear to signal adders

disable_ramp(stage)

Disable ramp for a given stage.

get_pattern(stage='channel')

Read pattern from FPGA internal BRAM buffer :param stage: stage where write the pattern: jesd, channel or beamf

initialise(nof_inputs_per_fpga=16)

Initialise Pattern Generator with default incremental pattern

set_pattern(buff, stage='channel')

Write pattern in FPGA internal BRAM buffer :param buff: pattern buffer, each element represents an output value :param stage: stage where write the pattern: jesd, channel or beamf

set_random_pattern(stage='channel', seed=0)

Write a randmon pattern in FPGA internal BRAM buffer :param stage: stage where write the pattern: jesd, channel or beamf :param seed: seed for random number generator generator

set_shift(shift, stage)

Set the bit shift. If used in ‘beamf’ stage, the value is overridden to 4. :param stage: stage where to set bit shift :param shift: bit shift (divides the pattern by 2^shift)

set_signal_adder(adder_list, stage)

Set signal adder. For each signal its pattern is constructed by adding a value to the pattern of input 0. :param adder_list: list of 64 adder (one adder per each signal and muxed value = 16*4) :param stage: stage where write the pattern: jesd, channel or beamf

set_zero(zero, stage)

Set mask on specific antenna/polarisation. :param stage: stage where to set mask. :param zero: An integer (0-65535) used as a mask to disable the pattern on specific

antennas and polarizations. The same mask is applied to both FPGAs, supporting up to 8 antennas and 2 polarizations. The default value is 0.

start_pattern(stage)

Start pattern. :param stage: stage where start the pattern: jesd, channel or beamf

status_check()

Abstract method where all status checks should be performed :return: Firmware status

stop_pattern(stage)

Stop pattern. :param stage: stage where stop the pattern: jesd, channel or beamf