jesd

Overview

configure the JESD settings on the FPGA, that receives data from the ADC

Python Class & Methods Index

class pyfabil.plugins.tpm.jesd.TpmJesd(board, **kwargs)[source]

TpmJesd plugin

check_link_error_counter()[source]

check_link_error_status()[source]

check_qpll_lock_loss_counter(show_result=True)[source]

check_qpll_lock_status()[source]

check_resync_counter(show_result=True)[source]

check_sync_status()[source]

clean_up()[source]: Perform cleanup :return: Success

clear_error_counters()[source]

disable_all_lanes()[source]

enable_all_lanes()[source]

initialise()[source]: Initialise TpmJesd

jesd_core_check()[source]

jesd_core_restart()[source]

jesd_core_start(single_lane=False, octects_per_frame=None, lane_in_use=255, disable_core=False)[source]: !@brief This function performs the FPGA internal JESD core configuration and initialization procedure as implemented in ADI demo.

jesd_lane_zero(lanes)[source]

status_check()[source]: Perform status check :return: Status