# Version History

## Unreleased

## 0.8.1
* [[JANUS-351](https://jira.skatelescope.org/browse/JANUS-351)] Fix to XML2VHDL read the docs dependencies install

## 0.8.0
* [[JANUS-351](https://jira.skatelescope.org/browse/JANUS-351)] First version of auto generated XML documentation

## 0.7.0
* [[JANUS-401](https://jira.skatelescope.org/browse/JANUS-401)] Improve documentation focusing on XML2VHDL standalone - SKA-Low TPM usage moved to examples
* [[JANUS-293](https://jira.skatelescope.org/browse/JANUS-293)] Added a custom Sphinx extension jira_changelog to add hyperlinks to CHANGELOG.md at docs build time
* [[JANUS-293](https://jira.skatelescope.org/browse/JANUS-293)] Bumped Sphinx Version to >=8.1.3 < 9.0.0
* [[JANUS-293](https://jira.skatelescope.org/browse/JANUS-293)] Minimum Python version bumped from 3.9 to 3.10

## 0.6.5
* [[JANUS-225](https://jira.skatelescope.org/browse/JANUS-225)] Added checking of whitespaces in register names
* [[JANUS-232](https://jira.skatelescope.org/browse/JANUS-232)] Bumped version of SKA Sphinx Theme to 0.2.1 which uses monospace font for code blocks

## 0.6.4
* [[JANUS-232](https://jira.skatelescope.org/browse/JANUS-232)] Migrate XML2VHDL Confluence page to readthedocs

## 0.6.3
* [[JANUS-231](https://jira.skatelescope.org/browse/JANUS-231)] Migrate XML2VHDL to poetry pyproject.toml
* [[JANUS-234](https://jira.skatelescope.org/browse/JANUS-234)] Add SKAO release process to XML2VHDL

## 0.6.2
* [[MCCS-2307](https://jira.skatelescope.org/browse/MCCS-2307)] Support for Python3.11

## 0.6.1
* [[MCCS-2069](https://jira.skatelescope.org/browse/MCCS-2069)] Update Firmware Build Flow to Support Python 3.10, Numpy 2.X

## 0.6.0
* Migration from BitBucket, added README and CODEOWNERS
* [[MCCS-601](https://jira.skatelescope.org/browse/MCCS-601)] XML2VHDL Documentation
* Migrated to BSD 3-Clause License

## 0.5.0
* Added gen_tb_packages argument handling
* Corrected IC VHDL template to detect falling edge of bready/rready
* Removed default value of BRAM user clock port, added comment.
* Corrected length of compressed xml in hex file header
* Dropped XPM support due to limited support of RAM initialisation in XPM library
* Corrected asym_ram_tdp.vhd template
* Solve init RAM file constant not substituted
* Support replacement of constants in XML from argument declaration

## 0.4.1
* Added BOARD constant resolution in xml2vhdl.py and generic constants resolution in xml2ic.py
* Add new Xml2Vhdl class to aid generation directly from imported xml2vhdl module
* Using XPM for BRAM
* Minor change to VHDL templates, removed blanks

## 0.4.0
* Revert default behaviour for rst_out_en changes made by casperFPGA
* Fix to package builds on linux and windows result in differing paths
* Fix to incorrect regfile.css source when copying to generated html path
* Fix to VHDL templates missing from packaged xml2vhdl
* Synchronised templates to version used in ska_lfaa_firmware repo
* Slave class import correction
* Fix to the -l and -a arguments never printed to the console
* fix to requiring -l argument causes -h and -a options to fail
* Add new bus definition to handle casperFPGA reset out enable implementation for AXI4Lite

## 0.3.0
* Prepare xml2vhdl for packaging as a module
* Make input-files argument required
* Add support for pip based build installations for both windows and linux systems

## 0.2.6
* Asymmetrical ram, reset we out and test bench simulation packages

## 0.2.0
* Migrated from Python 2.7 to Python 3.6

## 0.1.16
* Replaced optparse with argparse

## 0.1.15
* Added parameter for bus prefix

## 0.1.14
* Added Wishbone code generation

## 0.1.13
* Major code rewrite

## 0.1.12
* corrected error when command line option -a is used (attribute list generation)

## 0.1.11
* -r command line option

## 0.1.10
* reimplemented hw_ignore attribute

## 0.1.9
* corrected single char input from user

## 0.1.8
* print BRAM check, check of BRAM init file in VHDL

## 0.1.7
* hw_dp_ram_init_file_check attribute for skipping ram init file existence check

## 0.1.6
* converted sys.exit() to sys.exit(1)

## 0.1.5
* dp_ram initilaization from bin/hex file

## 0.1.4
* dp_ram implementation
* simple test bench creation
* commented "hw_ignore" attribute
* recursive iteration on links
* command line parameters
* generic reset values
* templates modification for consistent line spacing
* rearranged template files read/write

## 0.1.3
* ipb mapping correction, substituted "." with "_"

## 0.1.2
* newline character management

## 0.1.1
* bus library reference correction

## 0.1.0
* first release