(generated_monitoring_points_io)= # IO (generated_monitoring_points_io_jesd_interface)= ## JESD Interface (generated_monitoring_points_io_jesd_interface_link_status)= ### Link Status **Description**: JESD204 lane synchronisation status as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. See [Xilinx JESD204 v7.2 Product Guide](https://docs.amd.com/v/u/en-US/pg066-jesd204#page=34). JESD Sync Status is ``True`` if both of the below conditions are met: * A SYSREF event has been captured. * Link SYNC achieved. - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `True` - **Cleared When Read**: No, these metrics are continuously evaluated by the Xilinx JESD204 core so are live measurements.
Developer info - **Tile Method**: `check_jesd_link_status` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **core_id** (*int*): Specify which JESD Core, 0, 1, or None for both cores - **Returns**: True if a SYSREF event has been captured and link SYNC is achieved (*bool*)

(generated_monitoring_points_io_jesd_interface_lane_error_count)= ### Lane Error Count (generated_monitoring_points_io_jesd_interface_lane_error_count_fpga0)= #### FPGA0 (generated_monitoring_points_io_jesd_interface_lane_error_count_fpga0_core0)= ##### Core0 **Description**: JESD204 link error count per lane as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. The FPGA0 JESD CORE0 link error count for the eight lanes managed by the first JESD core of the first FPGA. These correspond to the first four dual polarisation antennas. To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. See [Xilinx JESD204 v7.2 Product Guide](https://docs.amd.com/v/u/en-US/pg066-jesd204#page=39). - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `{'lane0': 0, 'lane1': 0, 'lane2': 0, 'lane3': 0, 'lane4': 0, 'lane5': 0, 'lane6': 0, 'lane7': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_lane_error_counter(fpga_id=0, core_id=0)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **core_id** (*int*): Specify which JESD Core, 0, 1, or None for both cores - **Returns**: dict of counts (*dict(int) with an entry for each FPGA, core and lane*) - **Tile Method to Clear**: `clear_jesd_error_counters(fpga_id=0)`

(generated_monitoring_points_io_jesd_interface_lane_error_count_fpga0_core1)= ##### Core1 **Description**: JESD204 link error count per lane as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. The FPGA0 JESD CORE1 link error count for the eight lanes managed by the second JESD core of the first FPGA. These correspond to the second four dual polarisation antennas. To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. See [Xilinx JESD204 v7.2 Product Guide](https://docs.amd.com/v/u/en-US/pg066-jesd204#page=39). - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `{'lane0': 0, 'lane1': 0, 'lane2': 0, 'lane3': 0, 'lane4': 0, 'lane5': 0, 'lane6': 0, 'lane7': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_lane_error_counter(fpga_id=0, core_id=1)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **core_id** (*int*): Specify which JESD Core, 0, 1, or None for both cores - **Returns**: dict of counts (*dict(int) with an entry for each FPGA, core and lane*) - **Tile Method to Clear**: `clear_jesd_error_counters(fpga_id=0)`

(generated_monitoring_points_io_jesd_interface_lane_error_count_fpga1)= #### FPGA1 (generated_monitoring_points_io_jesd_interface_lane_error_count_fpga1_core0)= ##### Core0 **Description**: JESD204 link error count per lane as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. The FPGA1 JESD CORE0 link error count for the eight lanes managed by the first JESD core of the second FPGA. These correspond to the third four dual polarisation antennas. To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. See [Xilinx JESD204 v7.2 Product Guide](https://docs.amd.com/v/u/en-US/pg066-jesd204#page=39). - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `{'lane0': 0, 'lane1': 0, 'lane2': 0, 'lane3': 0, 'lane4': 0, 'lane5': 0, 'lane6': 0, 'lane7': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_lane_error_counter(fpga_id=1, core_id=0)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **core_id** (*int*): Specify which JESD Core, 0, 1, or None for both cores - **Returns**: dict of counts (*dict(int) with an entry for each FPGA, core and lane*) - **Tile Method to Clear**: `clear_jesd_error_counters(fpga_id=1)`

(generated_monitoring_points_io_jesd_interface_lane_error_count_fpga1_core1)= ##### Core1 **Description**: JESD204 link error count per lane as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. The FPGA1 JESD CORE1 link error count for the eight lanes managed by the second JESD core of the second FPGA. These correspond to the forth four dual polarisation antennas. To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. See [Xilinx JESD204 v7.2 Product Guide](https://docs.amd.com/v/u/en-US/pg066-jesd204#page=39). - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `{'lane0': 0, 'lane1': 0, 'lane2': 0, 'lane3': 0, 'lane4': 0, 'lane5': 0, 'lane6': 0, 'lane7': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_lane_error_counter(fpga_id=1, core_id=1)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **core_id** (*int*): Specify which JESD Core, 0, 1, or None for both cores - **Returns**: dict of counts (*dict(int) with an entry for each FPGA, core and lane*) - **Tile Method to Clear**: `clear_jesd_error_counters(fpga_id=1)`

(generated_monitoring_points_io_jesd_interface_lane_status)= ### Lane Status **Description**: **TODO**: Remove this monitoring point. This is simply a consolidated boolean form of the JESD204 link error counts above. JESD204 link error summary per lane consolidated from the link error counts per lane as reported by the Xilinx JESD204 core within the FPGA firmware. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. The aggregated status considers the link error counts across all 32 lanes. See [Xilinx JESD204 v7.2 Product Guide](https://docs.amd.com/v/u/en-US/pg066-jesd204#page=39). - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `True` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_lane_status(fpga_id=None, core_id=None)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **core_id** (*int*): Specify which JESD Core, 0, 1, or None for both cores - **Returns**: True if all error counters are 0 (*bool*) - **Tile Method to Clear**: `clear_jesd_error_counters`

(generated_monitoring_points_io_jesd_interface_resync_count)= ### Resync Count (generated_monitoring_points_io_jesd_interface_resync_count_fpga0)= #### FPGA0 **Description**: A count of JESD resync events. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. The FPGA0 JESD resync event count for the sixteen lanes managed by the two JESD cores of the first FPGA. These correspond to the first eight dual polarisation antennas. To track any occurances of intermittent loss of the JESD SYNC, the FPGA increments a counter each time the FPGA detects a rising edge of the JESD SYNC. **NOTE**: To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. The resync count is shared between both JESD cores in each FPGA, operating on the boolean AND of the JESD SYNC from both cores. - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_resync_counter(fpga_id=0, show_result=False)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **show_result** (*bool*): prints error counts on logger - **Returns**: counter values (*dict(int) with an entry for each FPGA*) - **Tile Method to Clear**: `clear_jesd_error_counters(fpga_id=0)`

(generated_monitoring_points_io_jesd_interface_resync_count_fpga1)= #### FPGA1 **Description**: A count of JESD resync events. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. The FPGA1 JESD resync event count for the sixteen lanes managed by the two JESD cores of the second FPGA. These correspond to the second eight dual polarisation antennas. To track any occurances of intermittent loss of the JESD SYNC, the FPGA increments a counter each time the FPGA detects a rising edge of the JESD SYNC. **NOTE**: To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. The resync count is shared between both JESD cores in each FPGA, operating on the boolean AND of the JESD SYNC from both cores. - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_resync_counter(fpga_id=1, show_result=False)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **show_result** (*bool*): prints error counts on logger - **Returns**: counter values (*dict(int) with an entry for each FPGA*) - **Tile Method to Clear**: `clear_jesd_error_counters(fpga_id=1)`

(generated_monitoring_points_io_jesd_interface_qpll_status)= ### QPLL Status (generated_monitoring_points_io_jesd_interface_qpll_status_fpga0)= #### FPGA0 **Description**: Status of transciever quad QPLL which generates the high-speed serial clock required by JESD204 links. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. The current status and historical status of the FPGA0 JESD QPLL for the sixteen lanes managed by the two JESD cores of the first FPGA. These correspond to the first eight dual polarisation antennas. **Example:** **(** current_status, historical_status_counter **)** **current_status**: The current QPLL lock status. * True → The QPLL is locked as expected. * False → The QPLL is not currently locked. **historical_status_counter**: To detect transient loss of the QPLL lock that occurs for less than 1 second, there is also the historical loss of lock counter. This counts the number of loss of lock events since the last query. * 0 → No loss of QPLL lock events have occured since the last query. * N > 0 → N loss of QPLL lock events have occured since the last query. **NOTE**: To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. The QPLL is shared between both JESD cores in each FPGA. - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `(True, 0)` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_qpll_status(fpga_id=0, show_result=False)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **show_result** (*bool*): prints error counts on logger - **Returns**: (True, 0) if lock is up and no loss of lock (*dict of tuple with an entry for each FPGA*) - **Tile Method to Clear**: `clear_jesd_error_counters(fpga_id=0)`

(generated_monitoring_points_io_jesd_interface_qpll_status_fpga1)= #### FPGA1 **Description**: Status of transciever quad QPLL which generates the high-speed serial clock required by JESD204 links. The FPGA JESD204B receiver is the sync for the serialized output of the TPM AD9695 ADCs. The current status and historical status of the FPGA1 JESD QPLL for the sixteen lanes managed by the two JESD cores of the second FPGA. These correspond to the second eight dual polarisation antennas. **Example:** **(** current_status, historical_status_counter **)** **current_status**: The current QPLL lock status. * True → The QPLL is locked as expected. * False → The QPLL is not currently locked. **historical_status_counter**: To detect transient loss of the QPLL lock that occurs for less than 1 second, there is also the historical loss of lock counter. This counts the number of loss of lock events since the last query. * 0 → No loss of QPLL lock events have occured since the last query. * N > 0 → N loss of QPLL lock events have occured since the last query. **NOTE**: To process data from eight dual channel ADCs, each TPM FPGA has two identical IP cores each managing 8 JESD lanes. The QPLL is shared between both JESD cores in each FPGA. - **Groups**: ``io``, ``jesd_interface`` - **Reported By**: TPM FPGAs - **Expected**: `(True, 0)` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_jesd_qpll_status(fpga_id=1, show_result=False)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **show_result** (*bool*): prints error counts on logger - **Returns**: (True, 0) if lock is up and no loss of lock (*dict of tuple with an entry for each FPGA*) - **Tile Method to Clear**: `clear_jesd_error_counters(fpga_id=1)`

(generated_monitoring_points_io_ddr_interface)= ## DDR Interface (generated_monitoring_points_io_ddr_interface_initialisation)= ### Initialisation **Description**: Status of DDR4 initialization and calibration. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. If ``True``, initialization and calibration are complete and the user can safely initiate read and write requests from the client interface. See ``init_calib_complete`` in [Xilinx UltraScale Architecture FPGAs Memory Interface Solutions](https://www.xilinx.com/support/documents/ip_documentation/mig/v7_1/pg150-ultrascale-mis.pdf#page=213). - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: `True` - **Cleared When Read**: No, this metric is managed by the Xilinx Memory Interface which autonomously updates the status.
Developer info - **Tile Method**: `check_ddr_initialisation` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: True if initialisation complete (*bool*)

(generated_monitoring_points_io_ddr_interface_reset_counter)= ### Reset Counter (generated_monitoring_points_io_ddr_interface_reset_counter_fpga0)= #### FPGA0 **Description**: A count of FPGA0 DDR4 reset events. Each FPGA has its own independent DDR4 SDRAM. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. To track any occurances of intermittent loss of the DDR, the FPGA increments a counter each time the FPGA detects a falling edge of the DDR user logic reset. - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_ddr_reset_counter(fpga_id=0, show_result=False)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **show_result** (*bool*): prints error counts on logger - **Returns**: counter values (*dict*) - **Tile Method to Clear**: `clear_ddr_reset_counter(fpga_id=0)`

(generated_monitoring_points_io_ddr_interface_reset_counter_fpga1)= #### FPGA1 **Description**: A count of FPGA1 DDR4 reset events. Each FPGA has its own independent DDR4 SDRAM. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. To track any occurances of intermittent loss of the DDR, the FPGA increments a counter each time the FPGA detects a falling edge of the DDR user logic reset. - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_ddr_reset_counter(fpga_id=1, show_result=False)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **show_result** (*bool*): prints error counts on logger - **Returns**: counter values (*dict*) - **Tile Method to Clear**: `clear_ddr_reset_counter(fpga_id=1)`

(generated_monitoring_points_io_ddr_interface_rd_cnt)= ### Rd Cnt (generated_monitoring_points_io_ddr_interface_rd_cnt_fpga0)= #### FPGA0 **Description**: DDR interface status. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. A count of FPGA0 DDR4 read cycles. Each FPGA has its own independent DDR4 SDRAM. - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: Updating/Incrementing - **Cleared When Read**: No, the counters are continuously incremented and roll-over.
Developer info - **Tile Method**: `get_ddr_if_stat(fpga_id=0, key='rd_cnt')` - **Arguments:** - **key** (*str*): ddr_if register - **fpga_id** (*int*): FPGA 0 or FPGA 1 - **Returns**: ddr_if register contents (*int*)

(generated_monitoring_points_io_ddr_interface_rd_cnt_fpga1)= #### FPGA1 **Description**: DDR interface status. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. A count of FPGA1 DDR4 read cycles. Each FPGA has its own independent DDR4 SDRAM. - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: Updating/Incrementing - **Cleared When Read**: No, the counters are continuously incremented and roll-over.
Developer info - **Tile Method**: `get_ddr_if_stat(fpga_id=1, key='rd_cnt')` - **Arguments:** - **key** (*str*): ddr_if register - **fpga_id** (*int*): FPGA 0 or FPGA 1 - **Returns**: ddr_if register contents (*int*)

(generated_monitoring_points_io_ddr_interface_wr_cnt)= ### Wr Cnt (generated_monitoring_points_io_ddr_interface_wr_cnt_fpga0)= #### FPGA0 **Description**: DDR interface status. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. A count of FPGA0 DDR4 write cycles. Each FPGA has its own independent DDR4 SDRAM. - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: Updating/Incrementing - **Cleared When Read**: No, the counters are continuously incremented and roll-over.
Developer info - **Tile Method**: `get_ddr_if_stat(fpga_id=0, key='wr_cnt')` - **Arguments:** - **key** (*str*): ddr_if register - **fpga_id** (*int*): FPGA 0 or FPGA 1 - **Returns**: ddr_if register contents (*int*)

(generated_monitoring_points_io_ddr_interface_wr_cnt_fpga1)= #### FPGA1 **Description**: DDR interface status. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. A count of FPGA1 DDR4 write cycles. Each FPGA has its own independent DDR4 SDRAM. - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: Updating/Incrementing - **Cleared When Read**: No, the counters are continuously incremented and roll-over.
Developer info - **Tile Method**: `get_ddr_if_stat(fpga_id=1, key='wr_cnt')` - **Arguments:** - **key** (*str*): ddr_if register - **fpga_id** (*int*): FPGA 0 or FPGA 1 - **Returns**: ddr_if register contents (*int*)

(generated_monitoring_points_io_ddr_interface_rd_dat_cnt)= ### Rd Dat Cnt (generated_monitoring_points_io_ddr_interface_rd_dat_cnt_fpga0)= #### FPGA0 **Description**: DDR interface status. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. A count of valid FPGA0 DDR4 read cycles. Each FPGA has its own independent DDR4 SDRAM. - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: Updating/Incrementing - **Cleared When Read**: No, the counters are continuously incremented and roll-over.
Developer info - **Tile Method**: `get_ddr_if_stat(fpga_id=0, key='rd_dat_cnt')` - **Arguments:** - **key** (*str*): ddr_if register - **fpga_id** (*int*): FPGA 0 or FPGA 1 - **Returns**: ddr_if register contents (*int*)

(generated_monitoring_points_io_ddr_interface_rd_dat_cnt_fpga1)= #### FPGA1 **Description**: DDR interface status. The TPM DDR4 SDRAM is utilized during operation of the station beamformer and antenna buffer components. A count of valid FPGA1 DDR4 read cycles. Each FPGA has its own independent DDR4 SDRAM. - **Groups**: ``io``, ``ddr_interface`` - **Reported By**: TPM FPGAs - **Expected**: Updating/Incrementing - **Cleared When Read**: No, the counters are continuously incremented and roll-over.
Developer info - **Tile Method**: `get_ddr_if_stat(fpga_id=1, key='rd_dat_cnt')` - **Arguments:** - **key** (*str*): ddr_if register - **fpga_id** (*int*): FPGA 0 or FPGA 1 - **Returns**: ddr_if register contents (*int*)

(generated_monitoring_points_io_f2f_interface)= ## F2F Interface (generated_monitoring_points_io_f2f_interface_pll_status)= ### PLL Status **Description**: Status of transciever quad QPLL which generates the high-speed serial clock required by the FPGA-to-FPGA link. The current status and historical status of the FPGA-to-FPGA (F2F) QPLL. **Example:** **(** current_status, historical_status_counter **)** **current_status**: The current QPLL lock status. * True → The QPLL is locked as expected. * False → The QPLL is not currently locked. **historical_status_counter**: To detect transient loss of the QPLL lock that occurs for less than 1 second, there is also the historical loss of lock counter. This counts the number of loss of lock events since the last query. * 0 → No loss of QPLL lock events have occured since the last query. * N > 0 → N loss of QPLL lock events have occured since the last query. - **Groups**: ``io``, ``f2f_interface`` - **Reported By**: TPM FPGAs - **Expected**: `(True, 0)` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_f2f_pll_status(show_result=False)` - **Arguments:** - **core_id** (*int*): Specify which F2F Core, 0, 1, or None for both cores - **show_result** (*bool*): prints error counts on logger - **Returns**: (True, 0) if lock is up and no loss of lock (*dict of tuple with an entry for each core*) - **Tile Method to Clear**: `clear_f2f_pll_lock_loss_counter`

(generated_monitoring_points_io_f2f_interface_soft_error)= ### Soft Error **Description**: Number of FPGA-to-FPGA link SOFT errors as reported by the Xilinx Aurora core within the FPGA firmware. See [Xilinx Aurora 64B/66B v12.0 Product Guide](https://docs.amd.com/r/12.0-English/pg074-aurora-64b66b/Error-Signals-in-Aurora-64B/66B-Cores). Soft errors are those detected by the Aurora 64B/66B encoding method. These can be caused by equipment problems and channel noise. Unlike hard errors, soft errors do not usually lead to a reset of the link. - **Groups**: ``io``, ``f2f_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: No, soft errors are live, they are reported every clock cycle in which they are detected.
Developer info - **Tile Method**: `check_f2f_soft_errors` - **Returns**: soft_err register value (*int*)

(generated_monitoring_points_io_f2f_interface_hard_error)= ### Hard Error **Description**: Number of FPGA-to-FPGA link HARD errors as reported by the Xilinx Aurora core within the FPGA firmware. See [Xilinx Aurora 64B/66B v12.0 Product Guide](https://docs.amd.com/r/12.0-English/pg074-aurora-64b66b/Error-Signals-in-Aurora-64B/66B-Cores). Hard errors are those detected by monitoring the FPGA transceivers for hardware errors such as buffer overflow and loss of lock. When a hard error occurs, the Aurora core automatically resets itself and attempts to re-initialize. In most cases, this permits re-establishing the Aurora 64B/66B channel when the hardware issue causing the hard error is resolved. - **Groups**: ``io``, ``f2f_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: No, hard errors are live, they are reported every clock cycle in which they are detected. Likely if a hard error occurs, the tile must be re-initialised.
Developer info - **Tile Method**: `check_f2f_hard_errors` - **Returns**: hard_err register value (*int*)

(generated_monitoring_points_io_udp_interface)= ## UDP Interface (generated_monitoring_points_io_udp_interface_arp)= ### ARP **Description**: Check UDP 40GbE ARP Table has been populated correctly. The TPM FPGAs transmit data products as UDP packets to the Science Data Network (SDN) using 40GbE. Confirms that all valid (populated) entries in the TPM 40GbE ARP table are resolved with MAC addresses. **NOTE**: This is a non-destructive version of the method `check_arp_table` which is to be used during station initialise. **NOTE**: ARP table entries for 40GbE QSFP connections that were disabled at initialise via the ``active_40g_ports_setting`` or ``qsfp_detection`` setting are skipped. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `True` - **Cleared When Read**: No, the status is evaluated from the live ARP table contents.
Developer info - **Tile Method**: `check_udp_arp_table_status(show_result=False)` - **Arguments:** - **show_result** (*bool*): prints ARP table contents to logger - **Returns**: True if all populated ARP table entries are also resolved (*bool*)

(generated_monitoring_points_io_udp_interface_status)= ### Status **Description**: UDP 40GbE consolidated error status. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. UDP Status is ``True`` if all of the below conditions are met: * The link is UP - the UDP Physical Layer (PHY) virtual lanes are aligned. * There are no RX Cyclic Redundancy Check (CRC) errors. * There are no RX Bit Interleave Parity (BIP) errors. * There are no Physical Layer (PHY) 66B/64B RX decoding errors. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `True` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_status` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: True if link is up and error counters are 0 (*bool*) - **Tile Method to Clear**: `clear_udp_status`

(generated_monitoring_points_io_udp_interface_crc_error_count)= ### CRC Error Count (generated_monitoring_points_io_udp_interface_crc_error_count_fpga0)= #### FPGA0 **Description**: UDP 40GbE RX Cyclic Redundancy Check (CRC) errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. A count of FPGA0 RX CRC errors. RX CRC (Cyclic Redundancy Check) errors indicate corrupted Ethernet frames detected at Layer-2 (Data Link Layer) via a checksum mismatch, most commonly caused by Layer-1 (Physical Layer) issues like faulty cables or transceivers. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_crc_error_counter(fpga_id=0)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: counter values (*dict*) - **Tile Method to Clear**: `clear_udp_status(fpga_id=0)`

(generated_monitoring_points_io_udp_interface_crc_error_count_fpga1)= #### FPGA1 **Description**: UDP 40GbE RX Cyclic Redundancy Check (CRC) errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. A count of FPGA1 RX CRC errors. RX CRC (Cyclic Redundancy Check) errors indicate corrupted Ethernet frames detected at Layer-2 (Data Link Layer) via a checksum mismatch, most commonly caused by Layer-1 (Physical Layer) issues like faulty cables or transceivers. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_crc_error_counter(fpga_id=1)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: counter values (*dict*) - **Tile Method to Clear**: `clear_udp_status(fpga_id=1)`

(generated_monitoring_points_io_udp_interface_bip_error_count)= ### BIP Error Count (generated_monitoring_points_io_udp_interface_bip_error_count_fpga0)= #### FPGA0 **Description**: UDP 40GbE Bit Interleaved Parity (BIP) errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. A count of FPGA0 RX BIP errors. RX BIP (Bit Interleaved Parity) errors indicate bit-level corruption detected at Layer-1 (Physical Layer) via parity checks, most commonly caused by physical transmission issues like signal degreated caused by faulty cables or transceivers. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `{'lane0': 0, 'lane1': 0, 'lane2': 0, 'lane3': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_bip_error_counter(fpga_id=0)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: counter values (*dict of int with an entry for each FPGA and PHY lane*) - **Tile Method to Clear**: `clear_udp_status(fpga_id=0)`

(generated_monitoring_points_io_udp_interface_bip_error_count_fpga1)= #### FPGA1 **Description**: UDP 40GbE Bit Interleaved Parity (BIP) errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. A count of FPGA1 RX BIP errors. RX BIP (Bit Interleaved Parity) errors indicate bit-level corruption detected at Layer-1 (Physical Layer) via parity checks, most commonly caused by physical transmission issues like signal degreated caused by faulty cables or transceivers. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `{'lane0': 0, 'lane1': 0, 'lane2': 0, 'lane3': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_bip_error_counter(fpga_id=1)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: counter values (*dict of int with an entry for each FPGA and PHY lane*) - **Tile Method to Clear**: `clear_udp_status(fpga_id=1)`

(generated_monitoring_points_io_udp_interface_decode_error_count)= ### Decode Error Count (generated_monitoring_points_io_udp_interface_decode_error_count_fpga0)= #### FPGA0 **Description**: UDP 40GbE Physical Layer (PHY) 66B/64B decoding errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. A count of FPGA0 RX decode errors. PHY RX decode errors indicate failures in interpreting the incoming physical signal detected at Layer-1 (Physical Layer) due to invalid symbols or encoding violations, most commonly caused by severe signal integrity issues such as noise ot faulty cables or transceivers. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `{'lane0': 0, 'lane1': 0, 'lane2': 0, 'lane3': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_decode_error_counter(fpga_id=0)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: counter values (*dict of int with an entry for each FPGA and PHY lane*) - **Tile Method to Clear**: `clear_udp_status(fpga_id=0)`

(generated_monitoring_points_io_udp_interface_decode_error_count_fpga1)= #### FPGA1 **Description**: UDP 40GbE Physical Layer (PHY) 66B/64B decoding errors. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. A count of FPGA1 RX decode errors. PHY RX decode errors indicate failures in interpreting the incoming physical signal detected at Layer-1 (Physical Layer) due to invalid symbols or encoding violations, most commonly caused by severe signal integrity issues such as noise ot faulty cables or transceivers. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `{'lane0': 0, 'lane1': 0, 'lane2': 0, 'lane3': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_decode_error_counter(fpga_id=1)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: counter values (*dict of int with an entry for each FPGA and PHY lane*) - **Tile Method to Clear**: `clear_udp_status(fpga_id=1)`

(generated_monitoring_points_io_udp_interface_linkup_loss_count)= ### Linkup Loss Count (generated_monitoring_points_io_udp_interface_linkup_loss_count_fpga0)= #### FPGA0 **Description**: UDP 40GbE link loss status. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. A count of FPGA0 UDP link loss events. To track any occurances of intermittent loss of link-up, the FPGA increments a counter each time the FPGA detects the link is down by monitoring the UDP Physical Layer (PHY) virtual lanes are aligned signal. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_linkup_loss_counter(fpga_id=0, show_result=False)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **show_result** (*bool*): prints error counts on logger - **Returns**: counter values (*dict*) - **Tile Method to Clear**: `clear_udp_status(fpga_id=0)`

(generated_monitoring_points_io_udp_interface_linkup_loss_count_fpga1)= #### FPGA1 **Description**: UDP 40GbE link loss status. The TPM FPGAs in a station aggregate data into station beams and ultimately transmit data products to MCCS and CBF as UDP packets to the Science Data Network (SDN) using 40GbE. A count of FPGA1 UDP link loss events. To track any occurances of intermittent loss of link-up, the FPGA increments a counter each time the FPGA detects the link is down by monitoring the UDP Physical Layer (PHY) virtual lanes are aligned signal. - **Groups**: ``io``, ``udp_interface`` - **Reported By**: TPM FPGAs - **Expected**: `0` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_udp_linkup_loss_counter(fpga_id=1, show_result=False)` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **show_result** (*bool*): prints error counts on logger - **Returns**: counter values (*dict*) - **Tile Method to Clear**: `clear_udp_status(fpga_id=1)`

(generated_monitoring_points_io_data_router)= ## Data Router (generated_monitoring_points_io_data_router_status)= ### Status **Description**: Data router error flag status. The TPM supports sharing a single 40GbE QSFP connection between the two FPGAs, transmitting and receiving all UDP packets via a primary FPGA. The routing of all data to and from the FPGA-to-FPGA (F2F) interface and the active 40GbE UDP interface is managed by a component called the data router. The data router status is ``> 0`` if any of the below errors are detected: * The F2F to UDP Clock Domain Crossing FIFO (First-In, First-Out) is written when full. * The UDP to F2F Clock Domain Crossing FIFO is written when full. * The UDP TX Arbiter Packet FIFO for the primary FPGA's staton beam is full. * The UDP TX Arbiter Packet FIFO for the primary FPGA's LMC data is stalled. * The UDP TX Arbiter Packet FIFO for the secondary FPGA's staton beam and LMC data is full. * The UDP TX Payload FIFO is stalled. * The UDP RX Input Selector FIFO is written when full. - **Groups**: ``io``, ``data_router`` - **Reported By**: TPM FPGAs - **Expected**: `{'FPGA0': 0, 'FPGA1': 0}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_data_router_status` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: register values (*dict of int with an entry for each FPGA*) - **Tile Method to Clear**: `clear_data_router_status`

(generated_monitoring_points_io_data_router_discarded_packets)= ### Discarded Packets **Description**: Number of station beam packets discarded by the data router. The TPM supports sharing a single 40GbE QSFP connection between the two FPGAs, transmitting and receiving all UDP packets via a primary FPGA. The routing of all data to and from the FPGA-to-FPGA (F2F) interface and the active 40GbE UDP interface is managed by a component called the data router. **Example:** **[** rejected_packets, overflow_packets **]** **rejected_packets**: Packets that are discarded due to incorrect size. * 0 → No packets were rejected since the last query. * N > 0 → N packets were rejected since the last query. **overflow_packets**: Packets that are discarded due to the UDP RX Input Selector FIFO being full. * 0 → No packets overflows since the last query. * N > 0 → N packet overflows since the last query. - **Groups**: ``io``, ``data_router`` - **Reported By**: TPM FPGAs - **Expected**: `{'FPGA0': [0, 0], 'FPGA1': [0, 0]}` - **Cleared When Read**: Yes
Developer info - **Tile Method**: `check_data_router_discarded_packets` - **Arguments:** - **fpga_id** (*int*): Specify which FPGA, 0, 1, or None for both FPGAs - **Returns**: register values (*dict of list of counts with an entry for each FPGA*) - **Tile Method to Clear**: `clear_data_router_status`