=======================
Latency Test
=======================

Purpose
=======

This test ensures the latency between ADC sampling and the transmission of station beam SPEAD packets from the final TPM in a station is less than 10ms.

Methodology
===========

1. Start all beamformers
2. The DSP latency status is cleared.
3. For each FPGA, DSP latency is read from the firmware, and is compared with the min and max thresholds which by default is 2 and 10ms respectively. This is repeated by the number of iterations set in the execute argument. The average latency of each FPGA is also logged.
4. For each FPGA the DSP latency status in the firmware is checked, This ensures that no spead packet sent out has a latency of more than 10 ms.
5. Stops any beamformers that were started, returning them to their previous state