Tile

Overview

This is the class which contains methods for monitoring and control of TPM hardware boards. These methods are the basis for all TPM versions.

Note

Inheritance means TPM 1.6 and higher can have additional or different methods if overloaded.

Python Class & Methods Index

Hardware functions for the TPM 1.2 hardware.

class pyaavs.tile.Tile(ip='10.0.10.2', port=10000, lmc_ip='10.0.10.1', lmc_port=4660, sampling_rate=800000000.0, logger=None)

Tile hardware interface library.

property active_40g_port

beamformer_is_running()

Check if station beamformer is running.

Returns:

beamformer running status

Return type:

bool

static calculate_delay(current_delay, current_tc, target, margin)

Calculate delay for PPS pulse.

Parameters:

• current_delay (int) – Current delay

• current_tc (int) – Current phase register terminal count

• target (int) – target delay

• margin (int) – marging, target +-margin

Returns:

Modified phase register terminal count

Return type:

int

check_40g_test_result()

check_arp_table(timeout=30.0)

Check that ARP table has been resolved for all used cores. 40G interfaces use cores 0 (fpga0) and 1 (fpga1) and ARP ID 0 for beamformer, 1 for LMC. The procedure checks that all populated ARP entries have been resolved. If the QSFP has been disabled or link is not detected up, the check is skipped.

Parameters:

timeout (float) – Timeout in seconds

Returns:

ARP table status

Return type:

bool

check_communication()

Checks status of connection to TPM CPLD and FPGAs. Returns dictionary of connection status. Examples: - OK Status:

{‘CPLD’: True, ‘FPGA0’: True, ‘FPGA1’: True}

• TPM ON, FPGAs not programmed or TPM overtemperature self shutdown: {‘CPLD’: True, ‘FPGA0’: False, ‘FPGA1’: False}

• TPM OFF or Network Issue: {‘CPLD’: False, ‘FPGA0’: False, ‘FPGA1’: False}

Non-destructive version of tile tpm_communication_check

check_fpga_synchronization()

Checks various synchronization parameters.

Output in the log

Returns:

OK status

Return type:

bool

check_pending_data_requests()

Checks whether there are any pending data requests.

Returns:

true if pending requests are present

Return type:

bool

check_synchronised_data_operation(requested_timestamp=None)

Check if synchronise data operations between FPGAs is successful.

Parameters:

requested_timestamp – Timestamp written into FPGA timestamp request register, if None it will be read

from the FPGA register

Returns:

Operation success

Return type:

bool

check_valid_timestamp_request(daq_mode, fpga_id=None)

Check valid timestamp request for various modes modes supported: raw_adc, channelizer and beamformer

Parameters:

• daq_mode – string used to select which Flag register of the LMC to read

• fpga_id – FPGA_ID, 0 or 1. Default None will select both FPGAs

Returns:

boolean to indicate if the timestamp request is valid or not

Return type:

boolean

clear_lmc_data_request()

Clear LMC data request register. This would be normally self-cleared by the firmware, however in case of failed synchronisation, the firmware will not clear the register. In that case the request register can be cleared by software to allow the next data request to be executed successfully.

clear_timestamp_invalid_flag_register(daq_mode=None, fpga_id=None)

Clear invalid timestamp request register for selected fpga and for selected LMC request mode . Default clears all registers for all modes

Parameters:

• daq_mode – string used to select which Flag register of the LMC to read

• fpga_id – FPGA_ID, 0 or 1. Default None will select both FPGAs

compute_calibration_coefficients()

Compute the calibration coefficients and load them in the hardware.

configure_10g_core(core_id, src_mac=None, src_ip=None, dst_mac=None, dst_ip=None, src_port=None, dst_port=None)

Configure a 10G core.

Todo:

Legacy method. Check whether to be deleted.

Parameters:

• core_id – 10G core ID

• src_mac – Source MAC address

• src_ip – Source IP address

• dst_mac – Destination MAC address

• dst_ip – Destination IP

• src_port – Source port

• dst_port – Destination port

configure_40g_core(core_id=0, arp_table_entry=0, src_mac=None, src_ip=None, src_port=None, dst_ip=None, dst_port=None, rx_port_filter=None, netmask=None, gateway_ip=None)

Configure a 40G core.

Parameters:

• core_id – 40G core ID

• arp_table_entry – ARP table entry ID

• src_mac – Source MAC address

• src_ip – Source IP address

• dst_ip – Destination IP

• src_port – Source port

• dst_port – Destination port

• rx_port_filter – Filter for incoming packets

• netmask – Netmask

• gateway_ip – Gateway IP

configure_active_40g_ports(configuration)

Configure which of the two 40G QSFP ports is used. Options are:

• Port 1 Only: “port1-only” (lower TPM 40G port, labeled P1 on newer subracks)

• Port 2 Only: “port2-only” (upper TPM 40G port, labeled P2 on newer subracks)

• Both Port 1 and Port 2: “both-ports”

NOTE: TPM 1.2 hardware does not support single port operation. Configurion of the is_master register will be ignored by the FPGA & both ports will always be used.

configure_integrated_beam_data(integration_time=0.5, first_channel=0, last_channel=192)

Configure and start continuous integrated beam data.

Parameters:

• integration_time (float, optional) – integration time in seconds, defaults to 0.5

• first_channel (int, optional) – first channel

• last_channel (int, optional) – last channel

configure_integrated_channel_data(integration_time=0.5, first_channel=0, last_channel=512)

Configure and start continuous integrated channel data.

Parameters:

• integration_time (float, optional) – integration time in seconds, defaults to 0.5

• first_channel (int, optional) – first channel

• last_channel (int, optional) – last channel

connect(initialise=False, load_plugin=True, enable_ada=False, enable_adc=True, dsp_core=True, adc_mono_channel_14_bit=False, adc_mono_channel_sel=0)

Connect to the hardware and loads initial configuration.

Parameters:

• initialise (bool) – Initialises the TPM object

• load_plugin (bool) – loads software plugins

• enable_ada (bool) – Enable ADC amplifier (usually not present)

• enable_adc (bool) – Enable ADC

• dsp_core (bool) – Enable loading of DSP core plugins

• adc_mono_channel_14_bit (bool) – Enable ADC mono channel 14bit mode

• adc_mono_channel_sel (int) – Select channel in mono channel mode (0=A, 1=B)

current_station_beamformer_frame()

Query time of packets at station beamformer input. :return: current frame, in units of 256 ADC frames (276,48 us) :rtype: int

current_tile_beamformer_frame()

Query time of packets at tile beamformer input. :return: current frame, in units of 256 ADC frames (276,48 us) :rtype: int

define_spead_header(station_id, subarray_id, nof_antennas, ref_epoch=-1, start_time=0)

Define SPEAD header for last tile.

All parameters are specified by the LMC.

Parameters:

• station_id – Station ID

• subarray_id – Subarray ID

• nof_antennas (int) – Number of antennas in the station

• ref_epoch (int) – Unix time of epoch. -1 uses value defined in set_epoch

• start_time – start time (TODO describe better)

Returns:

True if parameters OK, False for error

Return type:

bool

equalize_preadu_gain(required_rms=20)

Equalize the preadu gain to get target RMS

erase_fpgas()

Erase FPGA configuration memory.

get_40g_core_configuration(core_id, arp_table_entry=0)

Get the configuration for a 40g core.

Parameters:

• core_id (int) – Core ID

• arp_table_entry (int) – ARP table entry to use

Returns:

core configuration

Return type:

dict

get_adc_rms(sync=False)

Get ADC power, immediate.

Parameters:

sync (bool) – Synchronise RMS read

Returns:

ADC RMS power

Return type:

list(float)

get_arp_table()

Check that ARP table has been populated in for all used cores. Returns a dictionary with an entry for each core present in the firmware Each entry contains a list of the ARP table IDs which have been resolved by the ARP state machine.

Returns:

list of populated core ids and arp table entries

Return type:

dict(list)

get_firmware_list()

Get information for loaded firmware :return: Firmware information dictionary for each loaded firmware :rtype: list(dict)

get_fpga0_temperature()

Get FPGA0 temperature :return: FPGA0 temperature :rtype: float

get_fpga1_temperature()

Get FPGA1 temperature :return: FPGA0 temperature :rtype: float

get_fpga_time(device)

Return time from FPGA.

Parameters:

device (Device) – FPGA to get time from

Returns:

Internal time for FPGA

Return type:

int

Raises:

LibraryError – Invalid value for device

get_fpga_timestamp(device=Device.FPGA_1)

Get timestamp from FPGA.

Parameters:

device (Device) – FPGA to read timestamp from

Returns:

PPS time

Return type:

int

Raises:

LibraryError – Invalid value for device

get_ip()

Get tile IP. :return: tile IP address :rtype: str

get_phase_terminal_count()

Get PPS phase terminal count.

Returns:

PPS phase terminal count

Return type:

int

get_pps_delay(enable_correction=True)

Get delay between PPS and 10 MHz clock. :param: enable_correction, enable PPS delay correction using value configured in the FPGA1 :type: bool

Returns:

delay between PPS and 10 MHz clock in 200 MHz cycles

Return type:

int

get_preadu_levels()

Get preADU attenuation levels.

Returns:

Attenuation levels corresponding to each ADC channel, in dB.

get_rx_adc_rms()

Get ADC power. :return: ADC RMS power :rtype: list(float)

get_station_id()

Get station ID :return: station ID programmed in HW :rtype: int

get_temperature()

Read board temperature. :return: board temperature :rtype: float

get_tile_id()

Get tile ID.

Returns:

programmed tile id

Return type:

int

has_preadu()

Check if tile has preADUs fitted.

Gets preadu attribute “is_present” for each preADU. Returns True if both are present, else False.

property info

initialise(station_id=0, tile_id=0, lmc_use_40g=False, lmc_dst_ip=None, lmc_dst_port=4660, lmc_integrated_use_40g=False, src_ip_fpga1=None, src_ip_fpga2=None, dst_ip_fpga1=None, dst_ip_fpga2=None, src_port=4661, dst_port=4660, dst_port_single_port_mode=4662, rx_port_single_port_mode=4662, netmask_40g=None, gateway_ip_40g=None, active_40g_ports_setting='port1-only', enable_adc=True, enable_ada=False, enable_test=False, use_internal_pps=False, pps_delay=0, time_delays=0, is_first_tile=False, is_last_tile=False, qsfp_detection='auto', adc_mono_channel_14_bit=False, adc_mono_channel_sel=0)

Connect and initialise.

Parameters:

• station_id (int) – station ID

• tile_id (int) – Tile ID in the station

• lmc_use_40g (bool) – if True use 40G interface to transmit LMC data, otherwise use 1G

• lmc_dst_ip (str) – destination IP address for LMC data packets

• lmc_dst_port (int) – destination UDP port for LMC data packets

• lmc_integrated_use_40g (bool) – if True use 40G interface to transmit LMC integrated data, otherwise use 1G

• src_ip_fpga1 (str) – source IP address for FPGA1 40G interface

• src_ip_fpga2 (str) – source IP address for FPGA2 40G interface

• dst_ip_fpga1 (str) – destination IP address for beamformed data from FPGA1 40G interface

• dst_ip_fpga2 (str) – destination IP address for beamformed data from FPGA2 40G interface

• src_port (int) – source UDP port for beamformed data packets

• dst_port (int) – destination UDP port for beamformed data packets

• enable_ada (bool) – enable adc amplifier, Not present in most TPM versions

• enable_adc (bool) – Enable ADC

• enable_test (bool) – setup internal test signal generator instead of ADC

• use_internal_pps (bool) – use internal PPS generator synchronised across FPGAs

• pps_delay (int) – PPS delay correction in 625ps units

• time_delays (list(int)) – time domain delays for 32 inputs

• is_first_tile (bool) – True if this tile is the first tile in the beamformer chain

• is_last_tile (bool) – True if this tile is the last tile in the beamformer chain

• qsfp_detection (str) –

  “auto” detects QSFP cables automatically, “qsfp1”, force QSFP1 cable detected, QSFP2 cable not detected “qsfp2”, force QSFP1 cable not detected, QSFP2 cable detected “all”, force QSFP1 and QSFP2 cable detected “flyover_test”, force QSFP1 and QSFP2 cable detected and adjust

  polarity for board-to-board cable

  ”none”, force no cable not detected

• adc_mono_channel_14_bit (bool) – Enable ADC mono channel 14bit mode

• adc_mono_channel_sel (int) – Select channel in mono channel mode (0=A, 1=B)

initialise_beamformer(start_channel, nof_channels)

Initialise tile and station beamformers for a simple single beam configuration.

Parameters:

• start_channel (int) – Initial channel, must be even

• nof_channels (int) – Number of beamformed spectral channels

• is_first (bool) – True for first tile in beamforming chain

• is_last (bool) – True for last tile in beamforming chain

is_programmed()

Check whether the TPM is connected and programmed.

Returns:

If the TPM is programmed

Return type:

bool

is_qsfp_module_plugged(qsfp_id=0)

Initialise firmware components.

Returns:

True when cable is detected

load_antenna_tapering(beam, tapering_coefficients)

tapering_coefficients is a vector of 16 values, one per antenna. Default (at initialization) is 1.0. :todo: modify plugin to allow for different beams.

Parameters:

• beam (int) – Beam index in range 0:47

• tapering_coefficients (list(int)) – Coefficients for each antenna

load_beam_angle(angle_coefficients)

Angle_coefficients is an array of one element per beam, specifying a rotation angle, in radians, for the specified beam. The rotation is the same for all antennas. Default is 0 (no rotation). A positive pi/4 value transfers the X polarization to the Y polarization. The rotation is applied after regular calibration.

Parameters:

angle_coefficients (list(float)) – Rotation angle, per beam, in radians

load_calibration_coefficients(antenna, calibration_coefficients)

Loads calibration coefficients. calibration_coefficients is a bi-dimensional complex array of the form calibration_coefficients[channel, polarization], with each element representing a normalized coefficient, with (1.0, 0.0) the normal, expected response for an ideal antenna. Channel is the index specifying the channels at the beamformer output, i.e. considering only those channels actually processed and beam assignments. The polarization index ranges from 0 to 3. 0: X polarization direct element 1: X->Y polarization cross element 2: Y->X polarization cross element 3: Y polarization direct element The calibration coefficients may include any rotation matrix (e.g. the parallitic angle), but do not include the geometric delay.

Parameters:

• antenna (int) – Antenna number (0-15)

• calibration_coefficients (list(float)) – Calibration coefficient array

load_pointing_delay(load_time=0, load_delay=64)

Delay is updated inside the delay engine at the time specified. If load_time = 0 load immediately applying a delay defined by load_delay

Parameters:

• load_time (int) – time (in ADC frames/256) for delay update

• load_delay (int) – delay in (in ADC frames/256) to apply when load_time == 0

print_fpga_firmware_information(fpga_id=0)

Print FPGA firmware information :param fpga_id: FPGA ID, 0 or 1 :type fpga_id: int

program_cpld(bitfile)

Program CPLD with specified bitfile. Use with VERY GREAT care, this might leave the FPGA in an unreachable state. TODO Wiser to leave the method out altogether and use a dedicated utility instead?

Parameters:

bitfile – Bitfile to flash to CPLD

Returns:

write status

program_fpgas(bitfile)

Program both FPGAs with specified firmware.

Parameters:

bitfile (str) – Bitfile to load

Raises:

LibraryError – bitfile is None type

read_cpld(bitfile='cpld_dump.bit')

Read bitfile in CPLD FLASH.

Parameters:

bitfile (str) – Bitfile where to dump CPLD firmware

reset_eth_errors()

select_method_to_check_valid_synchronised_data_request(daq_mode, t_request, fpga_id=None)

Checks if Firmware contains the invalid flag register that raises a flag during synchronisation error. If the Firmware has the register then it will read it to check that the timestamp request was valid. If the register is not present, the software method will be used to calculate if the timestamp request was valid

Parameters:

• daq_mode – string used to select which Flag register of the LMC to read

• t_request – requested timestamp. Must be more than current timestamp to be synchronised successfuly

• fpga_id – FPGA_ID, 0 or 1. Default None

send_beam_data(timeout=0, timestamp=None, seconds=0.2)

Send beam data from the TPM :param timeout: When to stop :param timestamp: When to send :param seconds: When to synchronise

send_channelised_data(number_of_samples=1024, first_channel=0, last_channel=511, timestamp=None, seconds=0.2)

Send channelised data from the TPM :param number_of_samples: Number of spectra to send :param first_channel: First channel to send :param last_channel: Last channel to send :param timestamp: When to start transmission :param seconds: When to synchronise

send_channelised_data_continuous(channel_id, number_of_samples=128, wait_seconds=0, timestamp=None, seconds=0.2)

Continuously send channelised data from a single channel :param channel_id: Channel ID :param number_of_samples: Number of spectra to send :param wait_seconds: Wait time before sending data :param timestamp: When to start :param seconds: When to synchronise

send_channelised_data_narrowband(frequency, round_bits, number_of_samples=128, wait_seconds=0, timestamp=None, seconds=0.2)

Continuously send channelised data from a single channel :param frequency: Sky frequency to transmit :param round_bits: Specify which bits to round :param number_of_samples: Number of spectra to send :param wait_seconds: Wait time before sending data :param timestamp: When to start :param seconds: When to synchronise

send_raw_data(sync=False, timestamp=None, seconds=0.2, fpga_id=None)

Send raw data from the TPM :param sync: Synchronised flag :param timestamp: When to start :param seconds: Delay :param fpga_id: Specify which FPGA should transmit, 0,1, or None for both FPGAs

send_raw_data_synchronised(timestamp=None, seconds=0.2)

Send synchronised raw data :param timestamp: When to start :param seconds: Period

set_beamformer_epoch(epoch)

Set the Unix epoch in seconds since Unix reference time.

Parameters:

epoch – Unix epoch for the reference time

Returns:

Success status

Return type:

bool

set_beamformer_regions(region_array)

Set frequency regions. Regions are defined in a 2-d array, for a maximum of 16 (48) regions. Each element in the array defines a region, with the form [start_ch, nof_ch, beam_index]

• start_ch: region starting channel (currently must be a

  multiple of 2, LS bit discarded)

• nof_ch: size of the region: must be multiple of 8 chans

• beam_index: beam used for this region, range [0:8)

Total number of channels must be <= 384 The routine computes the arrays beam_index, region_off, region_sel, and the total number of channels nof_chans, and programs it in the HW.

Parameters:

region_array (list(list(int))) – list of region array descriptors

set_c2c_burst()

Setting C2C burst when supported by FPGAs and CPLD.

set_channeliser_truncation(trunc, signal=None)

Set channeliser truncation scale for the whole tile or for individual ADC channels.

Parameters:

• trunc (int or list(int)) – Truncted bits, channeliser output scaled down by specified number of bits. May be a single value (same for all frequency channels) or list of 512 values.

• signal (int) – Input signal, 0 to 31. If None, apply to all

set_csp_rounding(rounding)

Set output rounding for CSP.

Parameters:

rounding – Number of bits rounded in final 8 bit requantization to CSP

Returns:

success status

Return type:

bool

set_default_eth_configuration(src_ip_fpga1=None, src_ip_fpga2=None, dst_ip_fpga1=None, dst_ip_fpga2=None, src_port=4661, dst_port=4660, channel2_dst_port=4662, channel2_rx_port=4662, netmask_40g=None, gateway_ip_40g=None, qsfp_detection='auto')

Set destination and source IP/MAC/ports for 40G cores.

This will create a loopback between the two FPGAs.

Parameters:

• src_ip_fpga1 (str) – source IP address for FPGA1 40G interface

• src_ip_fpga2 (str) – source IP address for FPGA2 40G interface

• dst_ip_fpga1 (str) – destination IP address for beamformed data from FPGA1 40G interface

• dst_ip_fpga2 (str) – destination IP address for beamformed data from FPGA2 40G interface

• src_port (int) – source UDP port for beamformed data packets

• dst_port (int) – destination UDP port for beamformed data packets

Returns:

core configuration

Return type:

dict

set_first_last_tile(is_first, is_last)

Defines if a tile is first, last, both or intermediate.

One, and only one tile must be first, and last, in a chain. A tile can be both (one tile chain), or none.

Parameters:

• is_first (bool) – True for first tile in beamforming chain

• is_last (bool) – True for last tile in beamforming chain

Returns:

success status

Return type:

bool

set_fpga_time(device, device_time)

Set Unix time in FPGA.

Parameters:

• device (Device) – FPGA to get time from

• device_time (int) – Internal time for FPGA

Raises:

LibraryError – Invalid value for device

set_lmc_download(mode, payload_length=1024, dst_ip=None, src_port=61648, dst_port=4660, netmask_40g=None, gateway_ip_40g=None)

Configure link and size of control data for LMC packets.

Parameters:

• mode (str) – “1g” or “10g”

• payload_length (int) – SPEAD payload length in bytes

• dst_ip (str) – Destination IP

• src_port (int) – Source port for integrated data streams

• dst_port (int) – Destination port for integrated data streams

set_lmc_integrated_download(mode, channel_payload_length, beam_payload_length, dst_ip=None, src_port=61648, dst_port=4660, netmask_40g=None, gateway_ip_40g=None)

Configure link and size of control data for integrated LMC packets.

Parameters:

• mode (str) – ‘1g’ or ‘10g’

• channel_payload_length (int) – SPEAD payload length for integrated channel data

• beam_payload_length (int) – SPEAD payload length for integrated beam data

• dst_ip (str) – Destination IP

• src_port (int) – Source port for integrated data streams

• dst_port (int) – Destination port for integrated data streams

set_multi_channel_dst_ip(dst_ip, destination_id)

Set destination IP for a multichannel destination ID :param dst_ip: Destination IP address :param destination_id: 40G destination ID

set_multi_channel_tx(instance_id, channel_id, destination_id)

Set multichannel transmitter instance :param instance_id: Transmitter instance ID :param channel_id: Channel ID :param destination_id: 40G destination ID

set_phase_terminal_count(value)

Set PPS phase terminal count.

Parameters:

value – PPS phase terminal count

set_pointing_delay(delay_array, beam_index)

Specifies the delay in seconds and the delay rate in seconds/seconds. The delay_array specifies the delay and delay rate for each antenna. beam_index specifies which beam is described (range 0:7). Delay is updated inside the delay engine at the time specified by method load_delay.

Parameters:

• delay_array (list(list(float))) – delay and delay rate for each antenna

• beam_index (int) – specifies which beam is described (range 0:7)

set_pps_sampling(target, margin)

Set the PPS sampler terminal count

Parameters:

• target (int) – target delay

• margin (int) – margin, target +- margin

set_preadu_attenuation(attenuation)

Set same preadu attenuation in all preadus

set_preadu_levels(levels)

Set preADU attenuation levels.

Parameters:

levels – Desired attenuation levels for each ADC channel, in dB.

set_station_id(station_id, tile_id)

Set station ID.

Parameters:

• station_id – Station ID

• tile_id – Tile ID within station

set_test_generator_pulse(freq_code, amplitude=0.0)

Test generator Gaussian white noise setting.

Parameters:

• freq_code (int) – Code for pulse frequency. Range 0 to 7: 16,12,8,6,4,3,2 times frame frequency

• amplitude (float) – Tone peak amplitude, normalized to 127.5 ADC units, resolution 0.5 ADU

set_time_delays(delays)

Set coarse zenith delay for input ADC streams. Delay specified in nanoseconds, nominal is 0.

Parameters:

delays (list(float)) – Delay in samples, positive delay adds delay to the signal stream

Returns:

Parameters in range

Return type:

bool

start_40g_test(single_packet_mode=False, ipg=32)

start_acquisition(start_time=None, delay=2, tpm_start_time=None)

Start data acquisition.

Parameters:

• start_time – Time for starting (seconds)

• delay – delay after start_time (seconds)

• tpm_start_time – TPM will act as if it is started at this time (seconds)

start_beamformer(start_time=0, duration=-1, scan_id=0, mask=1099511627775)

Start the beamformer. Duration: if > 0 is a duration in frames * 256 (276.48 us) if == -1 run forever

Parameters:

• start_time (int) – time (in ADC frames/256) for first frame sent

• duration (int) – duration in ADC frames/256. Multiple of 8

• scan_id (int) – ID of the scan, to be specified in the CSP SPEAD header

• mask (int) – Bitmask of the channels to be started. Unsupported by FW

Returns:

False for error (e.g. beamformer already running)

Rtype bool:

start_multi_channel_tx(instances, timestamp=None, seconds=0.2)

Start multichannel data transmission from the TPM :param instances: 64 bit integer, each bit addresses the corresponding TX transmitter :param seconds: synchronisation delay ID

stop_40g_test()

stop_beamformer()

Stop beamformer.

stop_channelised_data_continuous()

Stop sending channelised data

stop_data_transmission()

Stop all data transmission from TPM

stop_integrated_beam_data()

Stop transmission of integrated beam data.

stop_integrated_channel_data()

Stop transmission of integrated channel data.

stop_integrated_data()

Stop transmission of integrated data.

stop_multi_channel_tx()

Stop multichannel TX data transmission

switch_calibration_bank(switch_time=0)

Switches the loaded calibration coefficients at prescribed time If time = 0 switch immediately :param switch_time: time (in ADC frames/256) for delay update :type switch_time: int

sync_fpga_time(use_internal_pps=False)

Set UTC time to two FPGAs in the tile Returns when these are synchronised.

Parameters:

use_internal_pps (bool) – use internally generated PPS, for test/debug

synchronised_beamformer_coefficients(timestamp=None, seconds=0.2)

Synchronise beamformer coefficients download.

Parameters:

• timestamp – Timestamp to synchronise against

• seconds – Number of seconds to delay operation

synchronised_data_operation(seconds=0.2, timestamp=None)

Synchronise data operations between FPGAs.

Parameters:

• seconds – Number of seconds to delay operation

• timestamp – Timestamp at which tile will be synchronised

Returns:

timestamp written into FPGA timestamp request register

Return type:

int

test_generator_disable_tone(generator)

Test generator: disable tone. Set tone amplitude and frequency to 0

Parameters:

generator (int) – generator select. 0 or 1

test_generator_input_select(inputs)

Specify ADC inputs which are substitute to test signal. Specified using a 32 bit mask, with LSB for ADC input 0.

Parameters:

inputs (int) – Bit mask of inputs using test signal

test_generator_set_noise(amplitude=0.0, load_time=0)

Test generator Gaussian white noise setting.

Parameters:

• amplitude (float) – Tone peak amplitude, normalized to 26.03 ADC units, resolution 0.102 ADU

• load_time (int) – Time to start the tone.

test_generator_set_tone(generator, frequency=100000000.0, amplitude=0.0, phase=0.0, load_time=0)

Test generator tone setting.

Parameters:

• generator (int) – generator select. 0 or 1

• frequency (float) – Tone frequency in Hz

• amplitude (float) – Tone peak amplitude, normalized to 31.875 ADC units, resolution 0.125 ADU

• phase (float) – Initial tone phase, in turns

• load_time (int) – Time to start the tone.

tpm_communication_check()

Brute force check to make sure we can communicate with programmed TPM.

tpm_version()

Determine whether this is a TPM V1.2 or TPM V1.6 :return: TPM hardware version :rtype: string

wait_pps_event()

Wait for a PPS edge. Added timeout feture to avoid method to stuck.

Raises:

BoardError – Hardware PPS stuck

pyaavs.tile.connected(f)

Helper to disallow certain function calls on unconnected tiles.

Parameters:

f (callable) – the method wrapped by this helper

Returns:

the wrapped method

Return type:

callable